power stripes

Do you want to change width and spacing, metal selection for power rings or power vertical stripes? Anyway you can easily set those setting from gui , if you want to do it in command line, you can do this way.

 addStripe -direction vertical -nets {VSS VDD } -layer MET2 -width 3.1 -spacing 0.5 -set_to_set_distance 100 -snap_wire_center_to_grid Grid -block_ring_top_layer_limit MET3 -block_ring_bottom_layer_limit MET1 -padcore_ring_top_layer_limit MET3 -padcore_ring_bottom_layer_limit MET1 -max_same_layer_jog_length 1.2 -merge_stripes_value 0.7

For detail description of each of these switches you can do "man addStripe" in command line. This will give you manual on addStripe.  

 Hi Gops,

 The width, spacing, and layer of your power stripes really depends on your design. You want enough power routing so that you don't have too big an IR-drop, but not so much that there's no room left for signal routing. You'll need more striping for a wire-bond design than you will for flip-chip. It can depend on how dense your design is, the frequency, how many total metal layers, etc. 

 Here are a few basic guidelines though: your std cell rails will mostly likely be on metal1, but we do see std cell libraries that have rails on metal2. These rails are often referred to as followpins. So that layer is pretty much decided for you, based on your library. You probably don't want to use the next layer (2 or 3) for stripes, because you would likely be blocking routing access to your std cell pins. We typically start stripes on metal4 and have stripes on every layer from 4 up. We have found that thinner, more frequent stripes are better than thicker, less frequent stripes for routability. If your design is easy to route, a typical strategy is to have thick, frequent stripes on the top 2 layers, so that almost all of the top 2 layers is pwr/gnd. But not all designs can afford that. As for width and spacing, you want to pick numbers that are divisible by the routing pitch, so that your stripes are centered on routing tracks and do not "waste" the tracks on either side by being off-center. 

The best thing is to do an IR-drop analysis as early as possible to make sure you have enough power (don't forget to analyze VSS as well as VDD).

- Kari

I agree with Kari, and would like to add to her comments. Some of the new capabilities in Encounter8.1 make estimating power grid's width and pitch very easy. Have a look at Early Rail Analysis in Encounter. It uses Encounter Power System (the new VoltageStorm) to estimate the IR drop at floor and power planning stages very quickly. This way you could quickly prototype your power grid and analyze it. You do not even need to have instances placed, it does virtual connectivity and estimates IR drop. Pretty cool stuff!

Thanks

Mohammad

 Hi,

I have some question on ERA. I want to know how I can get the IrDrop at each node of the design. For example If I have two cells I want to know how much IrDrop does exists at each cell.

I also want to know the IR Drop of each node during the time (vcd file). Is it possible with ERA?

Thanks