power stripes

 Hi Gops,

 The width, spacing, and layer of your power stripes really depends on your design. You want enough power routing so that you don't have too big an IR-drop, but not so much that there's no room left for signal routing. You'll need more striping for a wire-bond design than you will for flip-chip. It can depend on how dense your design is, the frequency, how many total metal layers, etc. 

 Here are a few basic guidelines though: your std cell rails will mostly likely be on metal1, but we do see std cell libraries that have rails on metal2. These rails are often referred to as followpins. So that layer is pretty much decided for you, based on your library. You probably don't want to use the next layer (2 or 3) for stripes, because you would likely be blocking routing access to your std cell pins. We typically start stripes on metal4 and have stripes on every layer from 4 up. We have found that thinner, more frequent stripes are better than thicker, less frequent stripes for routability. If your design is easy to route, a typical strategy is to have thick, frequent stripes on the top 2 layers, so that almost all of the top 2 layers is pwr/gnd. But not all designs can afford that. As for width and spacing, you want to pick numbers that are divisible by the routing pitch, so that your stripes are centered on routing tracks and do not "waste" the tracks on either side by being off-center. 

The best thing is to do an IR-drop analysis as early as possible to make sure you have enough power (don't forget to analyze VSS as well as VDD).

- Kari

 Hi Gops,

 The width, spacing, and layer of your power stripes really depends on your design. You want enough power routing so that you don't have too big an IR-drop, but not so much that there's no room left for signal routing. You'll need more striping for a wire-bond design than you will for flip-chip. It can depend on how dense your design is, the frequency, how many total metal layers, etc. 

 Here are a few basic guidelines though: your std cell rails will mostly likely be on metal1, but we do see std cell libraries that have rails on metal2. These rails are often referred to as followpins. So that layer is pretty much decided for you, based on your library. You probably don't want to use the next layer (2 or 3) for stripes, because you would likely be blocking routing access to your std cell pins. We typically start stripes on metal4 and have stripes on every layer from 4 up. We have found that thinner, more frequent stripes are better than thicker, less frequent stripes for routability. If your design is easy to route, a typical strategy is to have thick, frequent stripes on the top 2 layers, so that almost all of the top 2 layers is pwr/gnd. But not all designs can afford that. As for width and spacing, you want to pick numbers that are divisible by the routing pitch, so that your stripes are centered on routing tracks and do not "waste" the tracks on either side by being off-center. 

The best thing is to do an IR-drop analysis as early as possible to make sure you have enough power (don't forget to analyze VSS as well as VDD).

- Kari