swapping cells with HVT or LVT cells

The recommended way of optimizing leakage power concurrently with timing during the flow is as follows:

setOptMode -leakagePowerEffort {-none | -low | -high}
optDesign {-preCTS | -postCTS | -postRoute}

However, if you've got a design that meets timing postRoute and you'd like to optimize just leakage power without disrupting timing:

optLeakagePower -postRoute

-or-

setOptMode -leakagePowerEffort {-low | -high} -allowOnlyCellSwapping true
optDesign -postRoute

Hope this helps, Bob

Hi BobD,

 can we constrain encounter such that it will use  certain % of LVT cells?

Thanks,

Rahul

Not that I'm aware of.  I believe the algorithm seeks to use as many HVT as possible while maintaining timing.  The level of aggressiveness can be controlled with setOptMode -leakagePowerEffort {low | high}.

Is there a design rule or guideline that you're seeking to satisfy by controlling the percentage of LVT used?

 Rahul,

 I would be curious to find out why you want to constrain the %LVT cells? There is no reason the tools and most respectable optmization engines should stop reclaiming power if it does not penalize your other design goals. This is a common practice that was used and it generally yields suboptimal results. The issue is that the end-goal of the user is a given power target and whether tool achieves the desired goal using fancy optmizations or any % of any VT cells is "generally" inconsequential. Some design flows and ASIC vendors have predicated such guidelines as rules of thumb but ultimately if your target power is 1W that is all your driving towards. Modern Low Power optimization techniques have made it such that there are many techniques beyond multiVT to address low power issues as well. I highly recommned the low power guide published by Si2 (specially since it is free ;) ). IBM has also published papers at CDNLive and at SNUG highlighting flow trade-offs / options when using multiple VT libraries. In a Cadence flow, the recommendation is to use concurrent multi-VT optimization in RTL Compiler during synthesis and the options described by BobD in Encounter during the P&R portion of the flow

hope this helps,

gh-

 Hello,

Can you provide a flow to run SVT -> HVT swapping when routing is freeze and only swap is enabled ?

 David

 Did you try the optLeakagePower flows already mentioned in this thread?