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swapping cells with HVT or LVT cells

spach

can any explain the flow in encounter to swap the cell with hvt or lvt cells?

design is time closed, to reduce the leakage power i need to swap the cells with hvt cell so that i should not get any timing violatios

if there are any violations i can swap with lvt cells to aviod violations

please explain me the flow in encounter to achieve that

regards

suresh 

 

Parents

  •  Rahul,

     I would be curious to find out why you want to constrain the %LVT cells? There is no reason the tools and most respectable optmization engines should stop reclaiming power if it does not penalize your other design goals. This is a common practice that was used and it generally yields suboptimal results. The issue is that the end-goal of the user is a given power target and whether tool achieves the desired goal using fancy optmizations or any % of any VT cells is "generally" inconsequential. Some design flows and ASIC vendors have predicated such guidelines as rules of thumb but ultimately if your target power is 1W that is all your driving towards. Modern Low Power optimization techniques have made it such that there are many techniques beyond multiVT to address low power issues as well. I highly recommned the low power guide published by Si2 (specially since it is free ;) ). IBM has also published papers at CDNLive and at SNUG highlighting flow trade-offs / options when using multiple VT libraries. In a Cadence flow, the recommendation is to use concurrent multi-VT optimization in RTL Compiler during synthesis and the options described by BobD in Encounter during the P&R portion of the flow

     

    hope this helps,

    gh-

Reply

  •  Rahul,

     I would be curious to find out why you want to constrain the %LVT cells? There is no reason the tools and most respectable optmization engines should stop reclaiming power if it does not penalize your other design goals. This is a common practice that was used and it generally yields suboptimal results. The issue is that the end-goal of the user is a given power target and whether tool achieves the desired goal using fancy optmizations or any % of any VT cells is "generally" inconsequential. Some design flows and ASIC vendors have predicated such guidelines as rules of thumb but ultimately if your target power is 1W that is all your driving towards. Modern Low Power optimization techniques have made it such that there are many techniques beyond multiVT to address low power issues as well. I highly recommned the low power guide published by Si2 (specially since it is free ;) ). IBM has also published papers at CDNLive and at SNUG highlighting flow trade-offs / options when using multiple VT libraries. In a Cadence flow, the recommendation is to use concurrent multi-VT optimization in RTL Compiler during synthesis and the options described by BobD in Encounter during the P&R portion of the flow

     

    hope this helps,

    gh-

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