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Two sdc files and one design

tsahi
Hi friends,

My name is Tsahi, I am electronics student and beginner in place and route field.

One of the inputs of place and route is the timing constraints (sdc file).

In our mini project there are two sdc files:

1)  Pre cts  SDC file

2) Post cts SDC file

Can someone explain me why is the reason to make to two files and not use just single constraint file.

I attached the files to one zip file in comparing to each other (the left is pre cts, on the right hand post cts) and changes are marked.

Thanks,


Tsahi.
sdc.zip
Parents
  • BobD

    You're welcome!

    The first 2 items are minor (or perhaps meaningless depending on the caveats I mentioned in italics above). The 3rd item (set_clock_latency) is actually quite important and if not included it would invalidate your IO timing.

    Thanks,
    Bob

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  • BobD

    You're welcome!

    The first 2 items are minor (or perhaps meaningless depending on the caveats I mentioned in italics above). The 3rd item (set_clock_latency) is actually quite important and if not included it would invalidate your IO timing.

    Thanks,
    Bob

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