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Two sdc files and one design

tsahi
Hi friends,

My name is Tsahi, I am electronics student and beginner in place and route field.

One of the inputs of place and route is the timing constraints (sdc file).

In our mini project there are two sdc files:

1)  Pre cts  SDC file

2) Post cts SDC file

Can someone explain me why is the reason to make to two files and not use just single constraint file.

I attached the files to one zip file in comparing to each other (the left is pre cts, on the right hand post cts) and changes are marked.

Thanks,


Tsahi.
sdc.zip
Parents

  • I just wanted to mention that the set_propagated_clock statements can also be important if you're not using Restore Design to bring your data up in Encounter. Most of the time, we read in verilog, def, and SDC (Import Design, defin, loadTimingCon) and if it's a postCTS design, we need to have the set_propagated_clock lines in the SDC file. So we always have a postCTS SDC file, even if that's the only difference. (We call the preCTS file design.ideal.sdc and the postCTS file design.prop.sdc.)

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  • I just wanted to mention that the set_propagated_clock statements can also be important if you're not using Restore Design to bring your data up in Encounter. Most of the time, we read in verilog, def, and SDC (Import Design, defin, loadTimingCon) and if it's a postCTS design, we need to have the set_propagated_clock lines in the SDC file. So we always have a postCTS SDC file, even if that's the only difference. (We call the preCTS file design.ideal.sdc and the postCTS file design.prop.sdc.)

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