query on improving clock latency

 Hi Arun,

A good placement of flip flops will reduce latency i,e., sink pins of  a clock are not placed far away, so that latency is reduced. 

If ffs are falling far away group them and place them relatively closer.

thanks,

maven.

 Another thing you can do is use a nondefault rule for your clocks - most folks use double-wide, double-space. This may not help as much as a really good placement, as suggested above, but it's another trick in the bag.

 I just came across a couple of other things you could try: look in the docs at the setCTSMode options -optLatency and -optLatencyMoveGate. These are new in 8.1 - let us know how they work for you!

Great question! Reducing insertion delay is of course particularly important because it reduces the impact of timing derating on achieving timing closure.  Less insertion delay equals less effective derated clock skew, which makes it easier to achieve timign closure.

I asked around to some of my colleagues and have some additional suggestions to consider:

• Set a MaxDelay constraint of "0" in your clock tree spec file. This tends to task each stage of the clock tree building to focus more on insertion delay.  Note: I haven't tested this with the 8.1 setCTSMode -optLatency/-optLatencyMoveGate options Kari mentioned.
• Constraint the clock net routing to be on upper metal layers that are less resistive using the TopPreferredLayer and BottomPreferredLayer constructs.
• Check for the presence of FIXED, dont_touch or dont_use markings on instances and library cells (for example, clock gating cells) that exist in the clock network prior to calling CTS.
• Try to provide at least one strong driving cell candidate that CTS can use to drive a large fanout.
• Supply inverters to CTS rather than buffers.
• Use the MaxCap construct to help heavily loaded and therefore slower clock buffers.

Hi Bob,

Thank you for your response...

But if the max_delay constraint was kept as zero the buffers addition will be huge in number..

Thanks

-Arun 

Hi Arun,

Is that what you've observed? Or is that what you suspect would happen if you tried setting a MaxDelay of 0?

Thanks,
Bob

 A good selection of your fast inverters & buffers in the conf file also help.