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query on improving clock latency

abhaska

Hi all

Can anyone of you please share your views on improving clock latency in the CTS phase of the physical design flow.

Thanks

-Arun

Parents

  •  Another thing you can do is use a nondefault rule for your clocks - most folks use double-wide, double-space. This may not help as much as a really good placement, as suggested above, but it's another trick in the bag.

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  •  Another thing you can do is use a nondefault rule for your clocks - most folks use double-wide, double-space. This may not help as much as a really good placement, as suggested above, but it's another trick in the bag.

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