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Combinational Circuit In RTL Compiler

Kliatakis
Hello! I am a newbie in RTL compiler and SOC encounter and I would like to ask you a question. now that i have to deal with cores that have a clock the script that i run in RTL compiler is the following: read_hdl fpu_div.v elaborate dc::create _clock [dc::get_ports clk] -period 5 -waveform {0 2.5} dc::set_input_delay 1 -clock {clk} [dc::all_inputs] dc::set_output_delay 0.5 -clock {clk} [dc::all_outputs] dc::set_load 0.001 [dc::all_outputs] dc:: set_drive 1.2 [dc::all inputs] report timing > reports/repo_DP_FP_DIV report area >>reports/repo_DP_FP_DIV report power >> reports/repo_DP_FP_DIV write_sdc > sdc/sdc_rc_file_DP_FP_DIV write -mapped > netlists/DP_FP_DIV.v write_sdf > DP_FP_DIV_sdf If i have to deal with a core(for example a comparator) which is not clock triggered what do i have to do in RTL compiler? i do not use the commands that concern clock obviously, but do i have to put anything else?because if i do this i get this message: Warning : Possible timing problems have been detected in this design. [TIM-11] : The design is 'My_Comparator_128'. : Use 'report timing -lint' for more information. Thanks In advance!!!

  •  HiKiatakis,

     interestingly enough your script does not have synthesize command. Hopefully you missed it when you did cut & paste

    Also, is there any reason why you use dc:: instead of throwing your constraints in SDC file and reading with read_sdc ? 

    That way you will get the SDC summary statistics and error information in a much more useful manner.

    As per your comparator question, you can approach this in 2 ways:

    (1) Use SDC command set_max_delay or RC command path_delay

       In such case you would likely constraint from a given input/s to a given output/s

    (2) create a virtual clock and use as reference to all your inputs and outputs

    Approach (2) is most commonly used and is most efficient for most synthesis tools. An example in SDC syntax would look something like:

     create_clock -name my_clock -period 5

    set_input_delay 1.0 -clock my_clock [all_inputs]

    set_output_delay 2.0 -clock my_clock [all_outputs]

     good luck,

    gh-

     PS: RTL Compiler questions are best targeted or Logic Design forum; Encounter questions are better suited for this implementation forum

     

  • Yes the synthesize command disappeared during copy and paste...Thanks!!This is very helpful!
  • I did what you recommended with the sdc file...the question i have now is the following: how do i find out in Soc Encounter the maximum delay of my combinational circuit? i mean if i put in RTL compiler an output delay of 2 for example, then if i see in SOC encounter that timing is met that means that the delay of my circuit is less than 2?i am a bit confused :P thanks in advance!

  •  Hi Kliatakis,

     in the example provided earlier

    create_clock -name my_clock -period 5

    set_input_delay 1.0 -clock my_clock [all_inputs]

    set_output_delay 2.0 -clock my_clock [all_outputs]

    If timing is met it means that your delay is less than 2 ns (5 ns period - 1 ns input del. - 2 ns output del.)

    Now the real question is why would you need to synthesize a combinational block at such low level when RC

    can easily digest 1 million instances and it will prevent the budgeting nightmares of having to run things bottom-up

     gh-

     

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