Combinational Circuit In RTL Compiler

Hello! I am a newbie in RTL compiler and SOC encounter and I would like to ask you a question. now that i have to deal with cores that have a clock the script that i run in RTL compiler is the following: read_hdl fpu_div.v elaborate dc::create _clock [dc::get_ports clk] -period 5 -waveform {0 2.5} dc::set_input_delay 1 -clock {clk} [dc::all_inputs] dc::set_output_delay 0.5 -clock {clk} [dc::all_outputs] dc::set_load 0.001 [dc::all_outputs] dc:: set_drive 1.2 [dc::all inputs] report timing > reports/repo_DP_FP_DIV report area >>reports/repo_DP_FP_DIV report power >> reports/repo_DP_FP_DIV write_sdc > sdc/sdc_rc_file_DP_FP_DIV write -mapped > netlists/DP_FP_DIV.v write_sdf > DP_FP_DIV_sdf If i have to deal with a core(for example a comparator) which is not clock triggered what do i have to do in RTL compiler? i do not use the commands that concern clock obviously, but do i have to put anything else?because if i do this i get this message: Warning : Possible timing problems have been detected in this design. [TIM-11] : The design is 'My_Comparator_128'. : Use 'report timing -lint' for more information. Thanks In advance!!!