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What are tiehi and tielo cells?

NAADHAN

Hi all,

Please can any one explain me what are 'tiehi' and 'tielo' cells ? and how are they used in designing ?

 

 

Thanks & Regards,

NAADHAN

Parents

  • Well, tie cells can have even more benefits. But ESD is the main reason. Having the power/ground net connected to a fragile min size gate CMOS transistor is not ideal for high ESD requirements.
    For example, you can design a tie cell with metal mask programmable 0/1, which can be used for a small ROM in your design. Very practical. I'd recommend adding the tie cells during synthesis. But that's my personal preference.

    In RTL Compiler:

      insert_tiehilo_cells [-hilo <libcell>] [-hi <libcell>] [-lo <libcell>] [-all] [-maxfanout <integer>] [-verbose] [-skip_unused_hier_pins]  [<design|subdesign>] 

    Make sure you enable -skip_unused_hier_pins as you otherwise may get unnecessary floating tie cells. Use the -maxfanout to define how many gates the tie cell can drive. This is good for reducing the number of tie cells and thus area.

     

Reply

  • Well, tie cells can have even more benefits. But ESD is the main reason. Having the power/ground net connected to a fragile min size gate CMOS transistor is not ideal for high ESD requirements.
    For example, you can design a tie cell with metal mask programmable 0/1, which can be used for a small ROM in your design. Very practical. I'd recommend adding the tie cells during synthesis. But that's my personal preference.

    In RTL Compiler:

      insert_tiehilo_cells [-hilo <libcell>] [-hi <libcell>] [-lo <libcell>] [-all] [-maxfanout <integer>] [-verbose] [-skip_unused_hier_pins]  [<design|subdesign>] 

    Make sure you enable -skip_unused_hier_pins as you otherwise may get unnecessary floating tie cells. Use the -maxfanout to define how many gates the tie cell can drive. This is good for reducing the number of tie cells and thus area.

     

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