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  3. A problem with a BlackBox

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A problem with a BlackBox

meri
meri over 16 years ago

 Hi! I'm using a RAM of the AMS in my digital circuit. 

I've defined a blockbox with the line:  setImportMode -treatUndefinedCellAsBbox 1, and now I'm trying to load its floorPan (because I would like to see in the layout the metal of this block). These are the errors and warnings (they appears either if I load the floorPlan before then after defining the floorplan of the whole circuit):

**ERROR: Die Area is not defined
**WARN: Design Area's lower left corner is not on manufacture grid.
**WARN: Design Area's upper right corner is not on manufacture grid.
**ERROR: Incorrect width (0.00000)

Thanks a lot! 

 

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  • meri
    meri over 16 years ago

    Hi Kari,

    thanks again for your support!!!

    With your suggestion, now the connections between the RAM pins of power and ground to the ring are ok!

    Then, we've eliminated the command :

    setImportMode -treatUndefinedCellAsBbox 1

    because we have both the .lef (that defines the positions and the metal of the pins) and the .lib of the RAM (we've also the .fp, but I don't use it.. should I? and what do you mean with the OBS section of the ram lef?), so it's not a black box but I think it can be considered as an empty module; however, this hasn't avoided the routing of some metal connection on the "empty block" of the memory.

    Moreover, now we have a lot of DRC errors and antenna violations. We think that this can be caused by the connections between the pins of power supply and ground of the memory and the ring. These are made by stripes of metal 1 e 2, and they probably make the routing very hard and the congestion very high. We've tryied to use a lot of area (percentage of usage 30-40%), but the problems remain. Do you think the problem can be the floorpan? Or the some options of the special route? At the moment, we have a unique netlist, and we don't maintain the hierarchy (when we create the netlist after the logical synthesis) because we've seen that this gives problems of LVS (do you think that some versions of Encounter cannot support this?). So we have only one macro (the memory).

    Thank you very much!

    Happy Easter!

    Meri

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  • meri
    meri over 16 years ago

    Hi Kari,

    thanks again for your support!!!

    With your suggestion, now the connections between the RAM pins of power and ground to the ring are ok!

    Then, we've eliminated the command :

    setImportMode -treatUndefinedCellAsBbox 1

    because we have both the .lef (that defines the positions and the metal of the pins) and the .lib of the RAM (we've also the .fp, but I don't use it.. should I? and what do you mean with the OBS section of the ram lef?), so it's not a black box but I think it can be considered as an empty module; however, this hasn't avoided the routing of some metal connection on the "empty block" of the memory.

    Moreover, now we have a lot of DRC errors and antenna violations. We think that this can be caused by the connections between the pins of power supply and ground of the memory and the ring. These are made by stripes of metal 1 e 2, and they probably make the routing very hard and the congestion very high. We've tryied to use a lot of area (percentage of usage 30-40%), but the problems remain. Do you think the problem can be the floorpan? Or the some options of the special route? At the moment, we have a unique netlist, and we don't maintain the hierarchy (when we create the netlist after the logical synthesis) because we've seen that this gives problems of LVS (do you think that some versions of Encounter cannot support this?). So we have only one macro (the memory).

    Thank you very much!

    Happy Easter!

    Meri

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