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A problem with a BlackBox

meri

 Hi! I'm using a RAM of the AMS in my digital circuit. 

I've defined a blockbox with the line:  setImportMode -treatUndefinedCellAsBbox 1, and now I'm trying to load its floorPan (because I would like to see in the layout the metal of this block). These are the errors and warnings (they appears either if I load the floorPlan before then after defining the floorplan of the whole circuit):

**ERROR: Die Area is not defined
**WARN: Design Area's lower left corner is not on manufacture grid.
**WARN: Design Area's upper right corner is not on manufacture grid.
**ERROR: Incorrect width (0.00000)

Thanks a lot! 

 

  •  Is the RAM really still a black box? If so, you won't be able to see any metal. But, I have a feeling that the RAM is an existing design. In this case, the RAM vendor should be able to give you a .lef and .lib file, which you will need to load as part of your .conf file. (If you compile the RAMs yourself, there should be options in the compiler to output these files.) The .lef file is the one that contains the size of the RAM, the pins (metal), and blockages. 

  • Hi!


    First af all thanks for you precious support!

    You`re right, we have the .lef and the .lib of the RAM (obtained by a compiler). But in Cadence Virtuoso we can see not only the pin (pin metal 2 i.e.), but also the metal connected to the pin. In Encounter, on the contrary, we see only the pins. Then, we have other two problems:
    1) Encounter doesn`t connect the power supply and ground pins of the memory respectively to the nets vdd! e gnd! . So, there is a short-circuit between ground and power supply made by a filler cell, placed between one of the pins of power supply and one of those of ground, while the other pins (there are 3 pins for vdd and 3 for ground) are floating. This doesn`t happen for the inputs or the outputs.
    2) There is a metal routed in the space where has to be placed the memory (recognised as a "blackbox"): how can I avoid that Encounter routes any metal on the "blackbox"?

    Thanks again!

    Meri

  •  Hi Meri,

    Encounter is using the LEF, whereas Virtuoso uses the actual layout. LEF is an abstract of the layout, meaning it's not the full layout - just a representation of the important parts. It will have the pins, so you can route to them, but usually blockages where other metal is.

    If you have a LEF for the RAM, then it's not really a blackbox. I'm not sure what you mean when you say the ram is "recongized as a blackbox". Maybe your LEF is incomplete. If Encounter is routing over it, then it sounds like you are missing the blockage info (the OBS section of the RAM LEF). In most RAMS, you can route over them in the top couple of layers in your process, but you should not be able to route over them in all layers. Turn on Cell Blockage in your Encounter window and then turn the metal layers on and off, one by one, to see what blockages exist.

    As for the pwr/gnd pins, you need to use Sroute to connect the RAM pwr/gnd pins to your grid. (Route->Special Route) The "Block Pins" option is what you want; see the settings for Block Pins on the Advanced Tab and select All Pins.

    I'm not sure what's going on with the filler cell and the short - could you send a picture of that?

    - Kari

  • Hi Kari,

    thanks again for your support!!!

    With your suggestion, now the connections between the RAM pins of power and ground to the ring are ok!

    Then, we've eliminated the command :

    setImportMode -treatUndefinedCellAsBbox 1

    because we have both the .lef (that defines the positions and the metal of the pins) and the .lib of the RAM (we've also the .fp, but I don't use it.. should I? and what do you mean with the OBS section of the ram lef?), so it's not a black box but I think it can be considered as an empty module; however, this hasn't avoided the routing of some metal connection on the "empty block" of the memory.

    Moreover, now we have a lot of DRC errors and antenna violations. We think that this can be caused by the connections between the pins of power supply and ground of the memory and the ring. These are made by stripes of metal 1 e 2, and they probably make the routing very hard and the congestion very high. We've tryied to use a lot of area (percentage of usage 30-40%), but the problems remain. Do you think the problem can be the floorpan? Or the some options of the special route? At the moment, we have a unique netlist, and we don't maintain the hierarchy (when we create the netlist after the logical synthesis) because we've seen that this gives problems of LVS (do you think that some versions of Encounter cannot support this?). So we have only one macro (the memory).

    Thank you very much!

    Happy Easter!

    Meri

  •  Meri,

    You would only use a .fp file of the RAM if you are currently designing the RAM itself in Encounter. If the RAM is a macro in your block or chip, all the physical info is represented by the LEF file. It still sounds like the blockages aren't right. Look inside the RAM LEF for the OBS section. Do you see anything there?

    As for the DRC issues, it's hard to know what's going on without a picture. When you say antenna violations, do you mean process antennas or geometry antennas? It sounds like you mean geometry antennas.

    - Kari

  •  Kari,

    thanks to your advises I solved a lot of my problems related to the AMS memory import in Encounter!

    I found in Encounter two kinds of violations (off grid and process antenna, not geometry antenna) but  when I imported the layout in Cadence Virtuoso and performed the DRC (with ASSURA) these violations vanished. Note that I'm performing a DRC with all the options (coverage, erc, antenna...)

    Moreover I found that the LVS performed with ASSURA gives a positive result even if I delete a link to a pin of the memory. In other words it seems that the LVS does not control the connections to the memory block. I tried also to perform a LVS with ASSURA with the option BlackBoxCell but the problem remains.

    Have you got any ideas about this problem?

    Thanks a lot for your support!!!!

    Meri

  •  Hi Meri,

    I'm glad you've been able to work through a lot of your problems!

    As for DRC, which grid are your offgrid violations related to? If it's the manufacturing grid, I would expect to see those in DRC as well, unless you snap to the grid when streaming in. If you mean routing grid violations, those are not real violations, so DRC would not flag those. Process antenna violations don't always match up between FE's verify antenna and signoff DRC, because sometimes it's difficult to model the antenna rules in the LEF. But we usually see the other scenario - FE says there are no process antenna violations, but DRC still finds some. I suppose your LEF antenna rules could be pessimistic.

    Unfortunately, I won't be able to help much with your Assura LVS question. But I would be concerned if I deleted a connection to a RAM and LVS still ran clean!

    Are there any Assura folks out there who can help with this question?

    - Kari

  •  Hi Kari.

    I was talking about routing grid violation, not manufactoringgrid violations. So it is normal that I found these kind of violations in Encounter and not in Virtuoso. 

    Furthermore, about LVS problems with ASSURA.... I was able to solve my problems! I had to select an option in ASSURA (BlakBockCell) and specify the cell (AMS RAM). Now the LVS controls every connections to the memory pins, included power supply and ground!

    Thank again for your support.

    Meri

  •  You're welcome, Meri!

    I'm glad you were able to solve your LVS issue.

     

    - Kari

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