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A problem with a BlackBox

meri

 Hi! I'm using a RAM of the AMS in my digital circuit. 

I've defined a blockbox with the line:  setImportMode -treatUndefinedCellAsBbox 1, and now I'm trying to load its floorPan (because I would like to see in the layout the metal of this block). These are the errors and warnings (they appears either if I load the floorPlan before then after defining the floorplan of the whole circuit):

**ERROR: Die Area is not defined
**WARN: Design Area's lower left corner is not on manufacture grid.
**WARN: Design Area's upper right corner is not on manufacture grid.
**ERROR: Incorrect width (0.00000)

Thanks a lot! 

 

Parents

  •  Hi Meri,

    I'm glad you've been able to work through a lot of your problems!

    As for DRC, which grid are your offgrid violations related to? If it's the manufacturing grid, I would expect to see those in DRC as well, unless you snap to the grid when streaming in. If you mean routing grid violations, those are not real violations, so DRC would not flag those. Process antenna violations don't always match up between FE's verify antenna and signoff DRC, because sometimes it's difficult to model the antenna rules in the LEF. But we usually see the other scenario - FE says there are no process antenna violations, but DRC still finds some. I suppose your LEF antenna rules could be pessimistic.

    Unfortunately, I won't be able to help much with your Assura LVS question. But I would be concerned if I deleted a connection to a RAM and LVS still ran clean!

    Are there any Assura folks out there who can help with this question?

    - Kari

Reply

  •  Hi Meri,

    I'm glad you've been able to work through a lot of your problems!

    As for DRC, which grid are your offgrid violations related to? If it's the manufacturing grid, I would expect to see those in DRC as well, unless you snap to the grid when streaming in. If you mean routing grid violations, those are not real violations, so DRC would not flag those. Process antenna violations don't always match up between FE's verify antenna and signoff DRC, because sometimes it's difficult to model the antenna rules in the LEF. But we usually see the other scenario - FE says there are no process antenna violations, but DRC still finds some. I suppose your LEF antenna rules could be pessimistic.

    Unfortunately, I won't be able to help much with your Assura LVS question. But I would be concerned if I deleted a connection to a RAM and LVS still ran clean!

    Are there any Assura folks out there who can help with this question?

    - Kari

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