Stats

  • Locked Locked
  • Replies 9
  • Subscribers 91
  • Views 19333
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

A problem with a BlackBox

meri

 Hi! I'm using a RAM of the AMS in my digital circuit. 

I've defined a blockbox with the line:  setImportMode -treatUndefinedCellAsBbox 1, and now I'm trying to load its floorPan (because I would like to see in the layout the metal of this block). These are the errors and warnings (they appears either if I load the floorPlan before then after defining the floorplan of the whole circuit):

**ERROR: Die Area is not defined
**WARN: Design Area's lower left corner is not on manufacture grid.
**WARN: Design Area's upper right corner is not on manufacture grid.
**ERROR: Incorrect width (0.00000)

Thanks a lot! 

 

Parents

  •  Kari,

    thanks to your advises I solved a lot of my problems related to the AMS memory import in Encounter!

    I found in Encounter two kinds of violations (off grid and process antenna, not geometry antenna) but  when I imported the layout in Cadence Virtuoso and performed the DRC (with ASSURA) these violations vanished. Note that I'm performing a DRC with all the options (coverage, erc, antenna...)

    Moreover I found that the LVS performed with ASSURA gives a positive result even if I delete a link to a pin of the memory. In other words it seems that the LVS does not control the connections to the memory block. I tried also to perform a LVS with ASSURA with the option BlackBoxCell but the problem remains.

    Have you got any ideas about this problem?

    Thanks a lot for your support!!!!

    Meri

Reply

  •  Kari,

    thanks to your advises I solved a lot of my problems related to the AMS memory import in Encounter!

    I found in Encounter two kinds of violations (off grid and process antenna, not geometry antenna) but  when I imported the layout in Cadence Virtuoso and performed the DRC (with ASSURA) these violations vanished. Note that I'm performing a DRC with all the options (coverage, erc, antenna...)

    Moreover I found that the LVS performed with ASSURA gives a positive result even if I delete a link to a pin of the memory. In other words it seems that the LVS does not control the connections to the memory block. I tried also to perform a LVS with ASSURA with the option BlackBoxCell but the problem remains.

    Have you got any ideas about this problem?

    Thanks a lot for your support!!!!

    Meri

Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.