I am not sure about what
means peak and average IR drop mode analysis in Encounter. What of
these two analysis modes should be considered for power plan
I have a small block
design (5K gates) operating at very low frequency (640 KHz) and there
is a big difference between the results of these two analysis modes:
worst IR drop average
analysis: 9.8035e-05 v
worst IR drop peak
analysis: 4.3088e-01 v
Is average analysis
frequency dependent? But voltage drop is not event dependent and so
can cause timing problems also at low frequencies?
Thanks in advance.
Hi Clsantos,I think it is impossible to optimise for peak analysis. Look at the peak current; you will need hurndreds of micro width power stripe.Take a look at data sheet for a RAM, and you can see that the peak read/write power is huge.To reduce the peak current, a method is to purposely de-skew the clock so that not all logic are toggling at the same time, but this method is not too popular. You can also put some moscap (as filler cell) to reduce the IR drop. Other methold are in the design, like not to write to all memories at once (e.g. during MBIST, don't test all memory at one go).Anyone has encountered problem with peak IR drop in real chip?Regards,Eng Han