Peak and average IR drop analysis mode

average analyis is frequency dependent and it is calculated over a clock period. Peak analysis is instantaneous peak voltage drop

li siang

Originally posted in cdnusers.org by lisiang

Hi Clsantos,

I think it is impossible to optimise for peak analysis. Look at the peak current; you will need hurndreds of micro width power stripe.

Take a look at data sheet for a RAM, and you can see that the peak read/write power is huge.

To reduce the peak current, a method is to purposely de-skew the clock so that not all logic are toggling at the same time, but this method is not too popular. You can also put some moscap (as filler cell) to reduce the IR drop. Other methold are in the design, like not to write to all memories at once (e.g. during MBIST, don't test all memory at one go).

Anyone has encountered problem with peak IR drop in real chip?

Regards,
Eng Han

Originally posted in cdnusers.org by EngHan

Hello EngHan,

I found only these definitions about peak and average IR drop analysis in Encounter documentation:
AVERAGE: Displays a gradient of the average IR drop during the entire analysis period. Use this type of analysis to identify potential areas of power deficiency within the design.
PEAK: Displays a gradient that shows the largest IR drop during the analysis period. Use this type of analysis to identify IR drop that is caused by local switching activity.
But these definitions don't clarify my doubts...
If average IR drop is calculated over an entire clock period, this analysis mode should mislead delay problems due voltage drop at low frequencies?
I think that if switching activity, and so voltage drop, will occur only at the time around clock event , so it is better consider peak than average IR drop analysis... Is it right?

Regards,
Cristiano.

Originally posted in cdnusers.org by clsantos

FE's peak IR drop analysis is pseudo dynamic analysis. It uses transition time to calculate instaneous current for IR drop analysis, but it does not consider C effect. It reports the worst IR drop at each wire/instance. The peak worst IR drop is much larger than what is reported in the average mode since transition time is much smaller than the clock cycle.

To optimize power structure, use the average mode. To reduce peak IR drop, sizing up the power wires won't do the job unless power consumption is small. In this case, decap is needed and VSDG can be used to perform the dynamic IR drop analysis.

Originally posted in cdnusers.org by elvis

Hello,

Considering your answers and information found in this article (http://www.soccentral.com/results.asp?CategoryID=488&EntryID=19453)
I think these different analysis modes should be used for:
Optimize power rings/stripes: Average/static analysis;
Insert DECAP cells or avoid that all logic switch at the same time: Peak/dynamic analysis.

However, concerning elvis' answer, if FE's peak IR drop analysis does not consider C effect thus the natural decoupling capacitance of power network is not considered. Besides that, this analysis will not take into account inserted DECAP cells. Are these assumptions correct?
So, what is the purpose of this FE's peak analysis?

Originally posted in cdnusers.org by clsantos

i think most of the static analysis tools (FE, VoltageStorm, AstroRail) do not consider C effect. Only if you run dynamic IR drop analyis will the tools (VSDG, PrimeRail, RedHawk..) consider the effect of decap & power buses C. So i don't see the point of checking staic IR drop using peak analysis mode.

li siang

Originally posted in cdnusers.org by lisiang

Hi Clsantos,

Coming back to the discussion earlier, power and IR drop are not the same. In your case, the average power is very low because of very long period. However, very low average power means very low "average IR drop", but it does not imply anyting on peak IR.

I think it is like this. Your design has to pass average IR drop by a margin or else your dynamic IR drop will fail. Average IR drop is still useful as it is fast to run, and is the only information you have when you do power planning.

Regards,
Eng Han

Originally posted in cdnusers.org by EngHan

Hi Eng Han,

That is the point! In my case the average power is very low because of very long period. Please, consider figure 1.

I think there are switching activity only in a period equal to the critical delay within a clock period. The average current and so the IR drop during this critical delay period will be higher than the average IR drop over the entire clock period. So, this higher IR drop during this short period can provoke timing violations.

Is a good practice to consider a clock period equal the critical delay only to evaluate this effect (not for power estimation)?

Regards,

Cristiano.