Gate level netlist from Verilog XL

From the error message, the netlister is not guided to stop at the standard cell level (INVX1, AND3X1, ...). Instead, it decended into the stdcells and couldn't find a valid view for the instances inside those stdcells.  Have you provided a stop view name to the netlister for those stdcells?

Tongju,

Thanks for your reply! I wonder which view I should provide to the netlister. I was told by someone else that a "verilog" view must be created for netlisting. Do you have any idea on generate a verilog view on std cell library....

The "verilog" view will be good enough for the netlister. One way to create it is to choose "Verilog_editor" as the Tool Name in the Create Cell View form (file->new->View in library manager). This kind of views will make SOC encounter and verilog simulators happy.

 For the purpose to have a stop view for the netlister to create netlist for SOC encounter, a simpler version may work fine. For example, you could just simply open the symbol view of a cell and save it as a new view with new name (for example, "soc") and then, put "soc" into your stop view list when you do the netlisting. You should be able to create a netlist without any problem!

 Tongju