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  3. Gate level netlist from Verilog XL

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Gate level netlist from Verilog XL

tswong
tswong over 16 years ago

I am trying to generate a verilog gate netlist from a cadence schematics with standard cells by Verlilog XL, but it always return with an errors on standard cell. Does anyone see this type of error before?

ERROR: Netlister: cannot find master of instance I0 in cell INVX1.
ERROR: Netlister: cannot find master of instance I0 in cell AND3X1.
ERROR: Netlister: cannot find master of instance I0 in cell AND2X1.

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  • Tongju
    Tongju over 16 years ago

    The "verilog" view will be good enough for the netlister. One way to create it is to choose "Verilog_editor" as the Tool Name in the Create Cell View form (file->new->View in library manager). This kind of views will make SOC encounter and verilog simulators happy.

     For the purpose to have a stop view for the netlister to create netlist for SOC encounter, a simpler version may work fine. For example, you could just simply open the symbol view of a cell and save it as a new view with new name (for example, "soc") and then, put "soc" into your stop view list when you do the netlisting. You should be able to create a netlist without any problem!

     Tongju

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  • Tongju
    Tongju over 16 years ago

    The "verilog" view will be good enough for the netlister. One way to create it is to choose "Verilog_editor" as the Tool Name in the Create Cell View form (file->new->View in library manager). This kind of views will make SOC encounter and verilog simulators happy.

     For the purpose to have a stop view for the netlister to create netlist for SOC encounter, a simpler version may work fine. For example, you could just simply open the symbol view of a cell and save it as a new view with new name (for example, "soc") and then, put "soc" into your stop view list when you do the netlisting. You should be able to create a netlist without any problem!

     Tongju

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