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Hard macros power routing issues

dbekiaris

Hello everybody,

 I import a design in SoC Encounter 7.1, where three hard macros (SRAMs) exist. The problem is that when I am trying to create the power stripes and connect them with the core rings to synthesize the power grid, the SRAM p/g pins cannot connect with the remaining power/ground network, although I have selected the proper metal layer from the .lef files of the macros. Is there anything possible to do for this? I tried also to align pins of the specified macros with the power/ground stripes, but it failed again. If it is possible, please help. Thank you very much in advance.

 

  •   try to set Sroute-> Advanced->Connect Corners of ring pins   validation

  • Hi dbekiaris,

    whether the problem is for few RAMS or is it for all RAMS. If it is for few RAMS the problem could be orientation of RAM pins. For example ram pins are in MET4 and conventional direction for MET4 is say vertical and RAM is placed in such a way that MET4 pins on RAM are horizontal and when you try to draw stripes over RAM in say MET5. They may not get connected.

    Anyway there is a command to form vias . we can use this command even after the powerplan is completed.

    Before this command select rams on which connection is required. 

    editPowerVia -add_vias 1 -selected_blocks 1 -top_layer MET6 -bottom_layer MET4 -orthogonal_only 1 .

    This is what i understood from problem you described. correct me if i misunderstand the problem and give bit more clarification. 

     

     

     

  • Hi  dbekiaris,

    Use this command for connecting stripes to Ram pins and let me know whether it solved your problem or provide more details about problem.

    editPowerVia -add_vias 1 -selected_blocks 1 -top_layer top_layer_name -bottom_layer  bottom_layer_name -orthogonal_only 1

    Thanks

    suraj

     

     

  • Hi surajece01 Thank you very much for your helpful and immediate response!However, the problem is that I propable do not need any power vias to be added, as far as the stripes I selected have been put at the metal layer where the VDD/VSS of SRAMS are also placed. So, I suppose there is no need for vias. The problem is that the power grid creation takes a lot of time and the messages during the execution are not that emcouraging (e.g. CPU time for FollowPin 0 seconds). Does this message means problems with the follopin connections ? Thank you very much again in advance. Kind Regards dbekiaris

  • Hello everybody again

     The aforementioned problem continues to occur. In perspective, what I am doing is to create the power ring around the core at first and after that, I am creating custom power rings around the perimeter of the hard macros at the design boundary, so that each of them is connected to the core ring. However, the result is always a failure. I don't know whether the hard macro lefs are responsible for this. I would be grateful if someone could help me with this, because I don't know where is the wrong step that leads to opens. Thank you very much in advance.

     Kind Regards

    dbekiaris

     

  •  dbekiaris,

    Can you attach a picture or drawing of what you are trying to do? And maybe the commands you are using? 

    - Kari

  • Hi Kari and thanks for answering! Here is the picture of the open violations, demonstrating the hard macros (floorplan view). I also followed the advise of rotating some of the macros so that the pins are aligned, but nothing changed. What I have done is to create first of all the core ring (M6/M5 metal layers). I have choosen these because the metal layer for VDD/VSS of macros is M5. Also, the stripe metal layer is M5, while the standard cell special pins are of M1. After the core ring, I created 4 block rings, each for one macro. The rings I created are custom and they seem to be attached to the core ring. However, I can't see why these opens occur. I would be grateful if you could help/advise me on this problem. Thank you very much in advance. The picture follows. Kind Regards dbekiaris

  • Thanks for the picture - I hate to ask again, but could you post a picture that is zoomed in to one particular problem area, so I can really see what your issue is? Also, another thing you can try is to draw the connection yourself, with the wire editor, and see what happens. This is a method we use a lot to figure out why sroute sometimes can't make a connection. Make sure DRC is turned on, so you can see any violations that may be preventing sroute from completing the connections.

  • Hi Kari, Thanks again for answering!Here is the detailed view of one of the macros (in a larger design now, but based on the same technology library). It seems that the pins are not very well located, because the opens are put inside the area of the macro. Therefore, the ring for the specific block should be redrawn. But how can somebody find out the location of pins for a hard macro, apart from creating a specific partition? Thank you very much in advance again! Kind Regards dbekiaris

  • I still can't really tell what the issue is. Could you make sure the pwr/gnd pins of the macro are displayed, along with the ring you want to connect to? It may help to annotate the picture with some comments - I recommend Jing for this - it's free and very easy to use. You can easily take a picture from your screen, then draw arrows, circles, add text, etc.

    http://jingproject.com/

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