More problems with Encounter Library Characterizer (ELC)

I had seem the same problem, what I did was create a file and named modelspice.sp where I added the folowwing lines:

simulator lang=spice
.LIB '/toto/design_kits/foundry/hspiceS/tech/bsim3v3.lib' typical

In the elccfg file I used:

MODEL="modelspice.sp"; 

 without LIB and CORNER definitions.

Otherwise, seems like the db_prepare read two times the same file or I am using the LIB and CORNER in a wrong way.

I hope that helps.

 Regards

Julian Pontes 

Dear Julian, Thank you so much. Your suggestion works when I do not include the following line in modelspice.sp because my hspice simulator can not recognize it. simulator lang=spice However, I found that ELC just does not produce data for internal fall_power in the output library file out.lib. Below are the internal power data produced by ELC. Do you have the same problem? Is there a solution for this? Looking forward to hearing from you. Thanks again.

Best regards, Rung-Bin

internal_power() { related_pin : "B"; when : "A";

rise_power(energy_template_7x7) { index_1 ("0.03, 0.1, 0.4, 0.9, 1.5, 2.2, 3"); index_2 ("0.00035, 0.021, 0.0385, 0.084, 0.147, 0.231, 0.3115"); values ( \ "0.00115, 0.067566, 0.124174, 0.271881, 0.475576, 0.74728, 1.00608", \ "0.001161, 0.067696, 0.124546, 0.271154, 0.476156, 0.748399, 1.00174", \ "0.001075, 0.06688, 0.123424, 0.271997, 0.476142, 0.74833, 1.00553", \ "0.001147, 0.067461, 0.124297, 0.269402, 0.47623, 0.748605, 1.00676", \ "0.001054, 0.067198, 0.124859, 0.272029, 0.47621, 0.748343, 1.00928", \ "0.001082, 0.067408, 0.124578, 0.2721, 0.476171, 0.748392, 0.993107", \ "0.001097, 0.067349, 0.123965, 0.271298, 0.476332, 0.748429, 1.00807"); }

fall_power(energy_template_7x7) { index_1 ("0.03, 0.1, 0.4, 0.9, 1.5, 2.2, 3"); index_2 ("0.00035, 0.021, 0.0385, 0.084, 0.147, 0.231, 0.3115"); values ( \ "0, 0, 0, 0, 0, 0, 0", \ "0, 0, 0, 0, 0, 0, 0", \ "0, 0, 0, 0, 0, 0, 0", \ "0, 0, 0, 0, 0, 0, 0", \ "0, 0, 0, 0, 0, 0, 0", \ "0, 0, 0, 0, 0, 0, 0", \ "0, 0, 0, 0, 0, 0, 0"); }

Hi Rung-Bin,

Do you have achieve 100% of sucess on the vector simulation?

Another question, even in the rise_power the values shows a strange variation.

Did you use a cell to generate a nonlinear input slew?

The unique tip that I can get is to use spectre, maybe there is a malfunction between ELC and hspice. 

Best Regards, Julian

Dear Julian,

Thank so much for your help. I got 100% of success. A section of printout from my elc execution is attached below (in between with marks HSPICE-Start and HSPICE-End). I also try as you suggested using spectre simulator and using spectre model file. In eight simulation runs, four runs succeed and the other four fail as shown below ( in between with marks HSPICE-Start and HSPICE-End). for  those which fail, I found that spectre simulator can not recoginze a ".measure" statement even if there is a line "simulator lang=spice" before it. I really can not understand why this could happen and do not know what to do next. Any clue to these problems would be a great help. Thank again for your kind help.

Best regards,

Rung-Bin

***HSPICE-Start

    DESIGN        PROCESS       #ID         STATUS     IPDB
-------------+-------------+----------+--------------+-----------
AND2X1         typical       D0000         SIMULATE     basic_char
AND2X1         typical       D0001         SIMULATE     basic_char
AND2X1         typical       D0002         SIMULATE     basic_char
AND2X1         typical       D0003         SIMULATE     basic_char
AND2X1         typical       D0004         SIMULATE     basic_char
AND2X1         typical       D0005         SIMULATE     basic_char
AND2X1         typical       D0006         SIMULATE     basic_char
AND2X1         typical       D0007         SIMULATE     basic_char
============|=============|=============|==========|==============
AND2X1         typical       8          8            basic_char
-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
               Simulation Summary
-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
-------------+-------------+----------+--------------+-----------
-------------+-------------+----------+------------+-----------+------------
   DESIGN    |   PROCESS   |   #ID    |   STAGE    |  STATUS   |    IPDB
-------------+-------------+----------+------------+-----------+------------
AND2X1         typical       D0000     VERIFICATE   PASS        basic_char
AND2X1         typical       D0001     VERIFICATE   PASS        basic_char
AND2X1         typical       D0002     VERIFICATE   PASS        basic_char
AND2X1         typical       D0003     VERIFICATE   PASS        basic_char
AND2X1         typical       D0004     VERIFICATE   PASS        basic_char
AND2X1         typical       D0005     VERIFICATE   PASS        basic_char
AND2X1         typical       D0006     VERIFICATE   PASS        basic_char
AND2X1         typical       D0007     VERIFICATE   PASS        basic_char
-------------+-------------+----------+------------+----------

-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
 - Total Simulation : 8
 - Total Passed     : 8(100.00%)
 - Total Failed     : 0(0.00%)

****HSPICE-End

****SPECTRE-Start

    DESIGN        PROCESS       #ID         STATUS     IPDB
-------------+-------------+----------+--------------+-----------
AND2X1         typical       D0000         SIMULATE     basic_char
AND2X1         typical       D0001         SIMULATE     basic_char
AND2X1         typical       D0002         SIMULATE     basic_char
AND2X1         typical       D0003         SIMULATE     basic_char
AND2X1         typical       D0004         SIMULATE     basic_char
AND2X1         typical       D0005         SIMULATE     basic_char
AND2X1         typical       D0006         SIMULATE     basic_char
AND2X1         typical       D0007         SIMULATE     basic_char
============|=============|=============|==========|==============
AND2X1         typical       8          8            basic_char
-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
               Simulation Summary
-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
-------------+-------------+----------+--------------+-----------
-------------+-------------+----------+------------+-----------+------------
   DESIGN    |   PROCESS   |   #ID    |   STAGE    |  STATUS   |    IPDB
-------------+-------------+----------+------------+-----------+------------
AND2X1         typical       D0000     SIMULATE     FAIL        basic_char
AND2X1         typical       D0001     VERIFICATE   PASS        basic_char
AND2X1         typical       D0002     SIMULATE     FAIL        basic_char
AND2X1         typical       D0003     VERIFICATE   PASS        basic_char
AND2X1         typical       D0004     SIMULATE     FAIL        basic_char
AND2X1         typical       D0005     VERIFICATE   PASS        basic_char
AND2X1         typical       D0006     SIMULATE     FAIL        basic_char
AND2X1         typical       D0007     VERIFICATE   PASS        basic_char
-------------+-------------+----------+------------+----------

[INFO(db_spice)] Check the encounterlc.log/<ipdb_name>/<DESIGN>_<PROCESS>_<ID>.log file to determine the cause of the failure. The SPICE simulation log file can be found in the /home/csrlin/elc/LibChar/encounterlc.work/<DESIGN>_<PROCESS>_<ID>/ directory.

-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
 - Total Simulation : 8
 - Total Passed     : 4(50.00%)
 - Total Failed     : 4(50.00%)
-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-

*SPECTRE-End

 The first tip is to run db_spice with -keep_log and -keep_wave options. This enable to debug the spice simulation using db_wave comand.

db_spice -keep_wave -keep_log 

db_wave -d AND2X1 -p typical -id D0000 

this command will show the first failed simulation waveform.

Since the circuit that you are trying do the characterization is a 2-input AND circuit, I guest the error may be the simulation time that you set in the setup file. It seems that it cover the the rise transition but not cover the fall for every capacitance load and slew time pair.

Simulation std_cell {
  transient   = 1.0n 50n 10p ; // this means that simulation will run from 1.0 n until 50n at 10ps steps.

You can run using the db_spice options and then use the db_wave command to see if the simulation time cover the fall or rise transition at the output of cell or you can set the simulation time to a large value, it will increase your simulation time but you will see if this is the problem.

If the problem described above holds, so you may change the size of your pull down network to equilibrate the rise and fall propagation and output slew. 

Hi ,

I am facing following type of error while running elc.:-

spice syntax warning : illegal line order or unknown  device.

I have the netlist file,elc configuration file ,setup file and model file.