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More problems with Encounter Library Characterizer (ELC)

RungBin
Hi, I run into more problems with ELC when executing db_prepare. The spice library file (coming from TSMC) which I used for ELC is no problem with hspice, but I run into the following problem while executing db_prepare. My previous problem posted on August 15 was using a spice library file whose subckt keywords are commented out. Hence, I am wondering whether ELC can deal with a subckt definition within a .LIB section in a SPICE library file. I am more curious about whether anyone else is using ELC. Thanks for your help. Best regards, Rung-Bin - including rf018.l : RF_MOS Reading SUBCKT:NMOS_RF Reading SUBCKT:PMOS_RF - including rf018.l : MOS_RF - including rf018.l : DIO_RF - including rf018.l : RF_MOS Reading SUBCKT:NMOS_RF [ERROR(db_prepare)] spice syntax error: NMOS_RF : redefinition of the subckt [ file = rf018.l, #line = 1552 ] => .SUBCKT nmos_rf D G S B lr=18.E-08 nr=64 wr=1.5E-6
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  •  The first tip is to run db_spice with -keep_log and -keep_wave options. This enable to debug the spice simulation using db_wave comand.

    db_spice -keep_wave -keep_log 

    db_wave -d AND2X1 -p typical -id D0000 

    this command will show the first failed simulation waveform.

    Since the circuit that you are trying do the characterization is a 2-input AND circuit, I guest the error may be the simulation time that you set in the setup file. It seems that it cover the the rise transition but not cover the fall for every capacitance load and slew time pair.

    Simulation std_cell {
      transient   = 1.0n 50n 10p ; // this means that simulation will run from 1.0 n until 50n at 10ps steps.

    You can run using the db_spice options and then use the db_wave command to see if the simulation time cover the fall or rise transition at the output of cell or you can set the simulation time to a large value, it will increase your simulation time but you will see if this is the problem.

    If the problem described above holds, so you may change the size of your pull down network to equilibrate the rise and fall propagation and output slew. 

Reply

  •  The first tip is to run db_spice with -keep_log and -keep_wave options. This enable to debug the spice simulation using db_wave comand.

    db_spice -keep_wave -keep_log 

    db_wave -d AND2X1 -p typical -id D0000 

    this command will show the first failed simulation waveform.

    Since the circuit that you are trying do the characterization is a 2-input AND circuit, I guest the error may be the simulation time that you set in the setup file. It seems that it cover the the rise transition but not cover the fall for every capacitance load and slew time pair.

    Simulation std_cell {
      transient   = 1.0n 50n 10p ; // this means that simulation will run from 1.0 n until 50n at 10ps steps.

    You can run using the db_spice options and then use the db_wave command to see if the simulation time cover the fall or rise transition at the output of cell or you can set the simulation time to a large value, it will increase your simulation time but you will see if this is the problem.

    If the problem described above holds, so you may change the size of your pull down network to equilibrate the rise and fall propagation and output slew. 

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