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Encounter "short" violations

superman321
[Repost from IC design forum] hi, I have some "short" errors on my VDD and GND rails when I check for "verify geometry" using encounter for PAR. The macro cells's GND and VDD are placed 'right' on the designated GND and VDD rails and still the tool somehow doesnt match it with the cells GND/VDD and it shows short violations on every damn cell for GND and VDD!..any sort of help will be greatly appreciated. Here is the exact error message from encounter: "special wire of NET GND & blockage of cell g170" thanks
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  • Kari

    First check that your pwr/gnd nets are set up correctly, either in the .conf file:

    set rda_Input(ui_pwrnet) {VDD}
    set rda_Input(ui_gndnet) {GND}
    set rda_Input(PIN:VDD:) {VDD}
    set rda_Input(PIN:GND:) {GND}
    set rda_Input(TIEHI::) {VDD}
    set rda_Input(TIELO::) {GND}

    or with globalNetConnect statements:

    globalNetConnect VDD -type pgpin -pin VDD    -inst * -all -override
    globalNetConnect VDD -type tiehi             -inst * -all -override
    globalNetConnect GND -type pgpin -pin GND    -inst * -all -override
    globalNetConnect GND -type tielo             -inst * -all -override

     

    Second, the error message sounds like it's between blockage of the macro and your pwr/gnd grid. Does the macro have actual pwr/gnd PINS where it overlaps with the grid? Maybe instead of overlapping with the grid, the grid should just touch the edge of the macro? Are the blockages the whole size of the macro, or in the shape and location of where pwr/gnd pins would normally be? It's hard to tell for sure which situation you're seeing without a picture, but hopefully some of these ideas will help.

     

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  • Kari

    First check that your pwr/gnd nets are set up correctly, either in the .conf file:

    set rda_Input(ui_pwrnet) {VDD}
    set rda_Input(ui_gndnet) {GND}
    set rda_Input(PIN:VDD:) {VDD}
    set rda_Input(PIN:GND:) {GND}
    set rda_Input(TIEHI::) {VDD}
    set rda_Input(TIELO::) {GND}

    or with globalNetConnect statements:

    globalNetConnect VDD -type pgpin -pin VDD    -inst * -all -override
    globalNetConnect VDD -type tiehi             -inst * -all -override
    globalNetConnect GND -type pgpin -pin GND    -inst * -all -override
    globalNetConnect GND -type tielo             -inst * -all -override

     

    Second, the error message sounds like it's between blockage of the macro and your pwr/gnd grid. Does the macro have actual pwr/gnd PINS where it overlaps with the grid? Maybe instead of overlapping with the grid, the grid should just touch the edge of the macro? Are the blockages the whole size of the macro, or in the shape and location of where pwr/gnd pins would normally be? It's hard to tell for sure which situation you're seeing without a picture, but hopefully some of these ideas will help.

     

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