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Encounter "short" violations

superman321
[Repost from IC design forum] hi, I have some "short" errors on my VDD and GND rails when I check for "verify geometry" using encounter for PAR. The macro cells's GND and VDD are placed 'right' on the designated GND and VDD rails and still the tool somehow doesnt match it with the cells GND/VDD and it shows short violations on every damn cell for GND and VDD!..any sort of help will be greatly appreciated. Here is the exact error message from encounter: "special wire of NET GND & blockage of cell g170" thanks

  • First check that your pwr/gnd nets are set up correctly, either in the .conf file:

    set rda_Input(ui_pwrnet) {VDD}
    set rda_Input(ui_gndnet) {GND}
    set rda_Input(PIN:VDD:) {VDD}
    set rda_Input(PIN:GND:) {GND}
    set rda_Input(TIEHI::) {VDD}
    set rda_Input(TIELO::) {GND}

    or with globalNetConnect statements:

    globalNetConnect VDD -type pgpin -pin VDD    -inst * -all -override
    globalNetConnect VDD -type tiehi             -inst * -all -override
    globalNetConnect GND -type pgpin -pin GND    -inst * -all -override
    globalNetConnect GND -type tielo             -inst * -all -override

     

    Second, the error message sounds like it's between blockage of the macro and your pwr/gnd grid. Does the macro have actual pwr/gnd PINS where it overlaps with the grid? Maybe instead of overlapping with the grid, the grid should just touch the edge of the macro? Are the blockages the whole size of the macro, or in the shape and location of where pwr/gnd pins would normally be? It's hard to tell for sure which situation you're seeing without a picture, but hopefully some of these ideas will help.

     

  • Kari, Thanks for the reply. bulls eye!...its is the error message btwn the macro and the Pwr/GND rails. I have OBS for M1 over the macro excluding the GND/VDD area. and the pins for the Gnd/ VDD are on the far left and the far right of the macro boundaries. here is the picture:
    enc.pdf

  •  Yep, that would do it! Are these std cells? You wouldn't normally see a complete M1 blockage like that in a std cell.

  • Kari, yes those are std. cells drawn by me and i wrote my own LEF file too as its a new technology. The placements & routing are right except of those "short" errors!..So, does it mean i move my gnd and Vdd pins away from the grid? or..

  •  I'm not sure if you have access to an abstract generator tool. That might make your job easier. For most std cells, you'll have M1 pins and some M1 blockages that are smaller shapes. But, I know nothing about your library - so the typical things may not apply. I would suggest trimming back the M1 blockage so that there is enough space between the blockage and the pwr/gnd pins, but you'll need to make sure that you're still covering everything you want to with the blockage. You could also try having the M1 cover even the pwr/gnd pins, and then run verify geometry with "allow pin in blockage", but I'm worried you may miss some real errors by doing that. 

  • Kari, thank you so much, reducing the M1 block on OBS did the trick!!!..thank once again!

  •  You're welcome! :-) Make sure to run a signoff DRC as soon as you can to verify that you won't have any violations to surprise you near the end of your design cycle.

  • Sure sure...I wouldn't have had this problem in first place had I got the abstract Gen to work!..unfortunately, I would never get the Abs Gen to work right!..there are some errors all the time!

  •  I'm sorry you've had trouble with the abstract tool! (I'm assuming you're referring to the Cadence abstract tool.) Creating abstracts for std cells should be pretty straightforward. Did you try posting your questions about what you were seeing, or contacting your local AE? 

  • Oh, yeah it is the cadence Abs Gen!!...and I havent posted any questions on this community!!!...i wil post the exact errors In a bit!...but, in general I believe the error is: "it cant realize the "layers""!

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