bottomup flow,how to make submodule ring and stripe can been see in top module

Hi -

I'm trying to figure out how to place and route a hierarchy with SOC Encounter (v5.2). I must be missing something because it shouldn't be this hard! What I've done is:

1 - Start by place and routing a core macro. This works fine. I have a vdd! and gnd! ring around the circuit. I generate DEF and Verilog and read this back in to dfII and it DRC's and LVS's just fine. I'd like to use this macro in another design as a pre-designed macro!

2 - In SOC I use lefOut with the -stripePin option to get a lef file with vdd! and gnd! pins. I also generate a .lib file using do_extract_model. (I've also tried generating the lef file by running abstract on the layout view from dfII - same behavior)

3 - In SOC in my top-level design I import the core.lef and core.lib files in addition to the other stuff for my top-level design. The core is instantiated in my structural verilog file. When this is imported I get a core block that I can place in the floorplan.

4 - I can pick up and place the block, put a halo around it, etc. All seems fine...

5 - HERE'S THE PROBLEM - when I do my power planning (rings and stripes), I can NOT get the power routing connected to this macro! I've tried with the macro as CLASS BLOCK in the lef, I've tried with the macro as CLASS RING in the lef. I've tried making the vdd! and gnd! ports also of CLASS RING. I've made sure that I'm selecting the block pins in sroute. I've even followed the convoluted power planning template flow in the dtmf tutorial included with SOC.

NOTHING WORKS. The power routing ends up connected to the pads, connected to the standard cell rows, and the stripes are connected to the standard cells rows. But, the stripes just end before they get to my core macro. They don't connect to it!

It seems as if the nanorouting for the signal pins also works fine. But, I can't get SOC to connect the vdd! and gnd! wires to my macro. This macro was placed and routed by SOC, and the lef and lib were also generated by SOC. It must be possible to use it in SOC!

Help! What am I doing wrong or what am I not doing that needs to be done to make this work?

Thanks!
-Erik

Hi -

I'm trying to figure out how to place and route a hierarchy with SOC Encounter (v5.2). I must be missing something because it shouldn't be this hard! What I've done is:

1 - Start by place and routing a core macro. This works fine. I have a vdd! and gnd! ring around the circuit. I generate DEF and Verilog and read this back in to dfII and it DRC's and LVS's just fine. I'd like to use this macro in another design as a pre-designed macro!

2 - In SOC I use lefOut with the -stripePin option to get a lef file with vdd! and gnd! pins. I also generate a .lib file using do_extract_model. (I've also tried generating the lef file by running abstract on the layout view from dfII - same behavior)

3 - In SOC in my top-level design I import the core.lef and core.lib files in addition to the other stuff for my top-level design. The core is instantiated in my structural verilog file. When this is imported I get a core block that I can place in the floorplan.

4 - I can pick up and place the block, put a halo around it, etc. All seems fine...

5 - HERE'S THE PROBLEM - when I do my power planning (rings and stripes), I can NOT get the power routing connected to this macro! I've tried with the macro as CLASS BLOCK in the lef, I've tried with the macro as CLASS RING in the lef. I've tried making the vdd! and gnd! ports also of CLASS RING. I've made sure that I'm selecting the block pins in sroute. I've even followed the convoluted power planning template flow in the dtmf tutorial included with SOC.

NOTHING WORKS. The power routing ends up connected to the pads, connected to the standard cell rows, and the stripes are connected to the standard cells rows. But, the stripes just end before they get to my core macro. They don't connect to it!

It seems as if the nanorouting for the signal pins also works fine. But, I can't get SOC to connect the vdd! and gnd! wires to my macro. This macro was placed and routed by SOC, and the lef and lib were also generated by SOC. It must be possible to use it in SOC!

Help! What am I doing wrong or what am I not doing that needs to be done to make this work?

Thanks!
-Erik