in a bottomup design flow , there is a submodule,it has its own power ring and stripe,
when load the submodule to top level, how to make toplevel know the submodule's ring and stripe, so when do Sroute, top level row and stripe will hook up the subblock ring and stripe correctly.
the submodule designed by FLAT Encounter flow with a speical digital library, it has IO row, POWR ring/stripe and core row.
right now I use lef2oa and oa2lef, I can see VDD and VSS pin,but I cannot see the RING and Stripe definition.
can somebody show me how to do this
After performing place and route for a block level design, extract a lef for that design using lefOut - command .
Ex: lefOut -stripePin -PGpinLayers block_top_routing_layer -specifyTopLayer block_top_routing_layer -5.6 outputfilename.lef
Use this lef in top level flow along with technolgy lef & physical lef . Then you will get power grid information and it is vissible when you turn on instance pin. The tool will acees the same info while doing top level information.
I use : lefOut -stripePin -PGpinLayers 1 2 -extractBlockPGPinLayers 1 2 sub_block0.lef
we do Sroute I add -stripeSCpinTarget boundaryWithPin option,since there are some space between my ring and block Boundary
after load into toplevel ,I can see the power row/stripe pin come out is on Metal1 (lef/right) Metal2(top)
but after power planing, see the power row is hook up but with METAL1 ,but it add METAL3 to hookup the hardmarco follow Power pin(VDD already hook up METAL1,why it add METAL3), and a lot open error with the blockwire and followpin
similar issue on another website:
Are your global nets defined correctly? If you turn on query mode (the Q button at the bottom of the Encounter GUI), and put your mouse over one of your block pwr/gnd pins, does the information at the bottom of the Encounter window show the right net connection? Can you draw a connection by hand without any violations?