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help ! about CTS insertion delay

icmaple

in my case, there is a clkgen module, which has many divider-clock generator. i specify AutoCTSRootPin at chip port, and when i do cts, encounter total insert about 10 ns delay upto Sinks , but Only in clkgen module ,there is 7ns delay .( 70% occupied)  

what reason can cause the issue?  thanks 

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  • I'm not sure I understand your question.  Are you saying that CTS is creating a tree with insertion delay that is too large (10ns when you'd like it to be more like 2ns?) and further a large percentage of the insertion delay is within one logical hierarchy?

    If so, you might want to have a look to see if there are instances/nets that are in the clkgen module that are marked dont_touch (or the instances are from cell masters marked dont_use/dont_touch in the .lib).  Perhaps CTS is unable to reduce delay within this module because it's being restricted by these markings.

    If this is off the mark, try re-phrasing the question.  Someone may be able to help if they understand better.

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  • I'm not sure I understand your question.  Are you saying that CTS is creating a tree with insertion delay that is too large (10ns when you'd like it to be more like 2ns?) and further a large percentage of the insertion delay is within one logical hierarchy?

    If so, you might want to have a look to see if there are instances/nets that are in the clkgen module that are marked dont_touch (or the instances are from cell masters marked dont_use/dont_touch in the .lib).  Perhaps CTS is unable to reduce delay within this module because it's being restricted by these markings.

    If this is off the mark, try re-phrasing the question.  Someone may be able to help if they understand better.

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