help ! about CTS insertion delay

I'm not sure I understand your question.  Are you saying that CTS is creating a tree with insertion delay that is too large (10ns when you'd like it to be more like 2ns?) and further a large percentage of the insertion delay is within one logical hierarchy?

If so, you might want to have a look to see if there are instances/nets that are in the clkgen module that are marked dont_touch (or the instances are from cell masters marked dont_use/dont_touch in the .lib).  Perhaps CTS is unable to reduce delay within this module because it's being restricted by these markings.

If this is off the mark, try re-phrasing the question.  Someone may be able to help if they understand better.

Thank BobD's heartful reply!   it is just what you understand. 

In my case, along clock path , SDC file contains some instances which set_dont_touch ( AND gate,  taltncax8tl ) and No set_dont_touch nets in clkgen moudle. another,  in clkpath, there are many mux2XL and OAIXL ( lower driver cells) . Maybe these issue large delay during CTS in the clkgen module.     is indeed it?

That could indeed limit CTS's ability to size instances that pre-exist in the clock network efficiently in order to reduce insertion delay.

You might want to try a run where you relieve all of the dont_touch markings in instances in the design (or at least under that module) even if that goes beyond what you're actually allowed to do in terms of manipulating the clock network.  Additionally, you might want to check to make sure that the library cells that these pre-instantiated gates reference don't have dont_use/dont_touch markings.  They often do (to stop data path optimization for inadvertently swapping into these cells) so it's an additional item that can impact CTS.  If you do these 2 experiments you could get a feel for whether they are what's causing your insertion delay to be so large.