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help ! about CTS insertion delay

icmaple

in my case, there is a clkgen module, which has many divider-clock generator. i specify AutoCTSRootPin at chip port, and when i do cts, encounter total insert about 10 ns delay upto Sinks , but Only in clkgen module ,there is 7ns delay .( 70% occupied)  

what reason can cause the issue?  thanks 

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  • Thank BobD's heartful reply!   it is just what you understand. 

    In my case, along clock path , SDC file contains some instances which set_dont_touch ( AND gate,  taltncax8tl ) and No set_dont_touch nets in clkgen moudle. another,  in clkpath, there are many mux2XL and OAIXL ( lower driver cells) . Maybe these issue large delay during CTS in the clkgen module.     is indeed it?

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  • Thank BobD's heartful reply!   it is just what you understand. 

    In my case, along clock path , SDC file contains some instances which set_dont_touch ( AND gate,  taltncax8tl ) and No set_dont_touch nets in clkgen moudle. another,  in clkpath, there are many mux2XL and OAIXL ( lower driver cells) . Maybe these issue large delay during CTS in the clkgen module.     is indeed it?

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