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help ! about CTS insertion delay

icmaple

in my case, there is a clkgen module, which has many divider-clock generator. i specify AutoCTSRootPin at chip port, and when i do cts, encounter total insert about 10 ns delay upto Sinks , but Only in clkgen module ,there is 7ns delay .( 70% occupied)  

what reason can cause the issue?  thanks 

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  • That could indeed limit CTS's ability to size instances that pre-exist in the clock network efficiently in order to reduce insertion delay.

    You might want to try a run where you relieve all of the dont_touch markings in instances in the design (or at least under that module) even if that goes beyond what you're actually allowed to do in terms of manipulating the clock network.  Additionally, you might want to check to make sure that the library cells that these pre-instantiated gates reference don't have dont_use/dont_touch markings.  They often do (to stop data path optimization for inadvertently swapping into these cells) so it's an additional item that can impact CTS.  If you do these 2 experiments you could get a feel for whether they are what's causing your insertion delay to be so large.

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  • That could indeed limit CTS's ability to size instances that pre-exist in the clock network efficiently in order to reduce insertion delay.

    You might want to try a run where you relieve all of the dont_touch markings in instances in the design (or at least under that module) even if that goes beyond what you're actually allowed to do in terms of manipulating the clock network.  Additionally, you might want to check to make sure that the library cells that these pre-instantiated gates reference don't have dont_use/dont_touch markings.  They often do (to stop data path optimization for inadvertently swapping into these cells) so it's an additional item that can impact CTS.  If you do these 2 experiments you could get a feel for whether they are what's causing your insertion delay to be so large.

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