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Is it possible to write out a wireload model from encounter?

gops
Can any body please tell me whether it’s possible to write out a wireload model from encounter based on the lef and ict files I have provided into encounter database so that I can use the same in RTL compiler while synthesizing? (I don’t have an RC400 license currently to do physical)

  • EDI can certainly write out wireload models but I am curious why you are not running with PLEs in RC. Those take advantage of LEF and capTable and do not require RC400. They usually provide equal or better results than custom wireload and are a lot less works since they do not require any tuning

     gh-

  • Hi gops,

    I believe you want to pose this question to the logic design forum. The long and short of it is that neither RC nor EDI recode state machines. Ultimately, this is a dangerous proposition since it could break testbenches and certainly affect formal verification. The goal is for the RTL to mimic what the netlist should be. Any reason not to gray encoude upfront in the RTL ?

    gh-

  • Hi gh;
    Thank you very much for the reply. I have already tried the PLE flow with LEF and cap table. What I'm trying to do now is a comparison between both the results, i.e. a PLE one and a wireload generated from encounter.
     
    Can you please tell me how to write out a wireload model from encounter?
     
    Thanks
    Gops

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