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Is it possible to write out a wireload model from encounter?

gops
Can any body please tell me whether it’s possible to write out a wireload model from encounter based on the lef and ict files I have provided into encounter database so that I can use the same in RTL compiler while synthesizing? (I don’t have an RC400 license currently to do physical)
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  • Hi gops,

    I believe you want to pose this question to the logic design forum. The long and short of it is that neither RC nor EDI recode state machines. Ultimately, this is a dangerous proposition since it could break testbenches and certainly affect formal verification. The goal is for the RTL to mimic what the netlist should be. Any reason not to gray encoude upfront in the RTL ?

    gh-

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  • Hi gops,

    I believe you want to pose this question to the logic design forum. The long and short of it is that neither RC nor EDI recode state machines. Ultimately, this is a dangerous proposition since it could break testbenches and certainly affect formal verification. The goal is for the RTL to mimic what the netlist should be. Any reason not to gray encoude upfront in the RTL ?

    gh-

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