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Reg static and dynamic Power Analysis

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Hi...

I would like to knwo the steps included in finding out Static and dynamic Power analysis in SoC Encounter 8.1

I have a design.v, design_synth.v, .lib file, .lef file, .sdf file .So please let me know how to get the power .. include the steps plz...

how can i view(from GUI) my IO pads on the chip... i also included .io file when i import my design.
 
Parents

  •  Ya i read the user guide 8.1 but i dnt know how to generate .vvcd file in cadence encounter /rtl compiler. Can you help me in generating .vcd file. I think if i have a .vcd file i will get my whole power analysis.

     

    i have a file naming design.io thats for my design naming all the pin locations like east west..e tc i loaded it when i imported my design at  IO assignment file. So if i import my io file i should be physically be able to seeri8 ?but i am nt able tosee it andi dnt have any errors or warnings when i import my design including all .lib , lef, .sdf, synthesied verilog file,top cell.

    So can you say me where i am going wrong ?

Reply

  •  Ya i read the user guide 8.1 but i dnt know how to generate .vvcd file in cadence encounter /rtl compiler. Can you help me in generating .vcd file. I think if i have a .vcd file i will get my whole power analysis.

     

    i have a file naming design.io thats for my design naming all the pin locations like east west..e tc i loaded it when i imported my design at  IO assignment file. So if i import my io file i should be physically be able to seeri8 ?but i am nt able tosee it andi dnt have any errors or warnings when i import my design including all .lib , lef, .sdf, synthesied verilog file,top cell.

    So can you say me where i am going wrong ?

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