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Reg static and dynamic Power Analysis

Music

Hi...

I would like to knwo the steps included in finding out Static and dynamic Power analysis in SoC Encounter 8.1

I have a design.v, design_synth.v, .lib file, .lef file, .sdf file .So please let me know how to get the power .. include the steps plz...

how can i view(from GUI) my IO pads on the chip... i also included .io file when i import my design.
 

  •  Have you reviewed the chapter in the Encounter User Guide called "Power and Rail Analysis"?

     As for the IOs not showing up - that's a weird one. Make sure there are no warnings or errors in the log during design import. I didn't think you could "include" an io file during design import - do you mean you load it after you import the design?

  •  Ya i read the user guide 8.1 but i dnt know how to generate .vvcd file in cadence encounter /rtl compiler. Can you help me in generating .vcd file. I think if i have a .vcd file i will get my whole power analysis.

     

    i have a file naming design.io thats for my design naming all the pin locations like east west..e tc i loaded it when i imported my design at  IO assignment file. So if i import my io file i should be physically be able to seeri8 ?but i am nt able tosee it andi dnt have any errors or warnings when i import my design including all .lib , lef, .sdf, synthesied verilog file,top cell.

    So can you say me where i am going wrong ?

  • Unfortunately, I have no experience with VCD files, but I know they are not created in Encounter. One is not required for power analysis - you can do a vectorless analysis, but if you still want to use a VCD file, I would suggest posting the question in the Logic Design forum.

    For your IOs - is this a chip or a block? Meaning, are you talking about actual IO pad cells, or IO pins? I'm guessing you've already zoomed in really close to make sure they're just not too small to show up when the whole design is fit to the Encounter window. Another thing to try is use the Design Browser to find one of your IO cells and select it, then hit Q to bring up the attributes form. Then you can see what coordinates the cell is placed at, and go to those coordinates for a look. Also try turning on all the objects and looking at the design in all 3 modes - floorplan, amoeba, and physical. This is a hard one to diagnose without having your design in front of me, but hopefully some of these suggestions will help.

  •  Thanks for your reply...Kari.

     

    I would like to know how can i run the power analysis with with out vector analysis.. can u say me the steps so that i can run the analysis and get bck to u...

  •  This is all covered in the User Guide (note that the Encounter User Guide refers you to the EPS User Guide chapters 5 - 12 for Signoff Analysis, but you can run all EPS functions through Encounter). I would only be repeating the steps from the guide. Please follow the Encounter or EPS User Guide, and post back to the forum if you come across a specific issue.

    Thanks!

     

  • Hello;

    There are two types of power analysis possible
    one is static which dont require a VCD or TCF (the tool assumes a default switching activity fo all nodes, which you can change) and
    other is dynamic which either requires a VCD file or Timing window file(TWF)
    For better analysis of power you have to do the dynamic power analysis.

    Regarding your problem that you are not seeing IOs on encounter
    Do you a have the IO PADs in your netlist?
    just check for them whether its available or not else include them.

    Now how to generate a VCD file in simulator (NCsim).I think VCD is not generated in RC, its generated frm simulator.You should have a good testbench which should have satisfactory functional coverage for the purpose .Other wise the power value maynot be the accurate one.

    For VHDL rtl Codes
    use the following procedure:

    ncsim >  call vcdfile filename.vcd

    ncsim >  call vcdaddscope : -a       

    ncsim >  call vcddumpvars

    ncsim >  run

    ncsim >  call vcdflush

    For verilog rtl codes
    use the following initial in your testbench:

    Below should be sufficient to dump all the signals inside testname and all the instantiations in this top module.


    initial

    begin

            $dumpfile("debug.vcd");
            $dumpvars(0, testname);

            $dumpall;
    end

     
    Please let me know if you have further questions .

     
    gops
  • Hello;
     
    There are two types of power analysis possible
    one is static which dont require a VCD or TCF (the tool assumes a default switching activity fo all nodes, which you can change) and
    other is dynamic which either requires a VCD file or Timing window file(TWF)
    For better analysis of power you have to do the dynamic power analysis.
     
    Regarding your problem that you are not seeing IOs on encounter
    Do you a have the IO PADs in your netlist?
    just check for them whether its available or not else include them.
     
    Now how to generate a VCD file in simulator (NCsim).I think VCD is not generated in RC, its generated frm simulator.You should have a good testbench which should have satisfactory functional coverage for the purpose .Other wise the power value maynot be the accurate one.
     
    For VHDL rtl Codes
    use the following procedure:
     
    ncsim >  call vcdfile filename.vcd
     
    ncsim >  call vcdaddscope : -a      
     
    ncsim >  call vcddumpvars
     
    ncsim >  run
     
    ncsim >  call vcdflush
     
    For verilog rtl codes
    use the following initial in your testbench:
     
    Below should be sufficient to dump all the signals inside testname and all the instantiations in this top module.
     
     
     
    initial
     
    begin
     
            $dumpfile("debug.vcd");
            $dumpvars(0, testname);
            $dumpall;
    end
     
     
     
    Please let me know if you have further questions .
     
     
    gops

  •  Hi..

      Thanks for your reply. I dnt have NCSIM . So is there any more chance for me to generate vcd file with modelsim/xilinx .. And i also need osme help in generating Power grid librarry i.e .cl file. Do you know hoew to generate ./ i saw the user guide but there was nothing regarding .cl file generation ? so if u can help me i will be really lucky. And comming to io pads, i dnt have my io pads in my netlist. So if u can say me how to include in the net list i would be really happy. With a small example for a 4 bit adder. or any other simple .verilog code.

  • Hello;

    I'm not sure about modelsim/xilinx.I think the following is enough for modelsim also.you can give it in modelsim prompt(VSIM) corresponding to ncsim in NC.I am not so familiar with modelsim,sorry if there is some error.

    vcd file myvcdfile.vcd

    vcd add /test_name/dut/*

    run

    quit -f

    But for generating powergrid views you need Encounter power system (EPS) license.Do you have EPS license?check the EPS documentation regarding .cl file generation.

    Regarding IO pad insertion there are two ways to do it.The simple way is to create another top level in RTL code, with ports connceted to IOcells and then synthesize.

    Another is reading the synthesized n/l in virtuso and insert padcells in virtouso and write out the pad inserted n/l ..

    I think you can use the first method. attached is a simple example how to create a top level with pad instantiation.I haven't checked the syntax of the code.there may be some errors.But i think this is enough to give you the idea.

    gops

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