Reg static and dynamic Power Analysis

Hello;
 
There are two types of power analysis possible
one is static which dont require a VCD or TCF (the tool assumes a default switching activity fo all nodes, which you can change) and
other is dynamic which either requires a VCD file or Timing window file(TWF)
For better analysis of power you have to do the dynamic power analysis.
 
Regarding your problem that you are not seeing IOs on encounter
Do you a have the IO PADs in your netlist?
just check for them whether its available or not else include them.
 
Now how to generate a VCD file in simulator (NCsim).I think VCD is not generated in RC, its generated frm simulator.You should have a good testbench which should have satisfactory functional coverage for the purpose .Other wise the power value maynot be the accurate one.
 
For VHDL rtl Codes
use the following procedure:
 
ncsim >  call vcdfile filename.vcd
 
ncsim >  call vcdaddscope : -a      
 
ncsim >  call vcddumpvars
 
ncsim >  run
 
ncsim >  call vcdflush
 
For verilog rtl codes
use the following initial in your testbench:
 
Below should be sufficient to dump all the signals inside testname and all the instantiations in this top module.
 
 
 
initial
 
begin
 
        $dumpfile("debug.vcd");
        $dumpvars(0, testname);
        $dumpall;
end
 
 
 
Please let me know if you have further questions .
 
 
gops

Hello;
 
There are two types of power analysis possible
one is static which dont require a VCD or TCF (the tool assumes a default switching activity fo all nodes, which you can change) and
other is dynamic which either requires a VCD file or Timing window file(TWF)
For better analysis of power you have to do the dynamic power analysis.
 
Regarding your problem that you are not seeing IOs on encounter
Do you a have the IO PADs in your netlist?
just check for them whether its available or not else include them.
 
Now how to generate a VCD file in simulator (NCsim).I think VCD is not generated in RC, its generated frm simulator.You should have a good testbench which should have satisfactory functional coverage for the purpose .Other wise the power value maynot be the accurate one.
 
For VHDL rtl Codes
use the following procedure:
 
ncsim >  call vcdfile filename.vcd
 
ncsim >  call vcdaddscope : -a      
 
ncsim >  call vcddumpvars
 
ncsim >  run
 
ncsim >  call vcdflush
 
For verilog rtl codes
use the following initial in your testbench:
 
Below should be sufficient to dump all the signals inside testname and all the instantiations in this top module.
 
 
 
initial
 
begin
 
        $dumpfile("debug.vcd");
        $dumpvars(0, testname);
        $dumpall;
end
 
 
 
Please let me know if you have further questions .
 
 
gops