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Reg static and dynamic Power Analysis

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Hi...

I would like to knwo the steps included in finding out Static and dynamic Power analysis in SoC Encounter 8.1

I have a design.v, design_synth.v, .lib file, .lef file, .sdf file .So please let me know how to get the power .. include the steps plz...

how can i view(from GUI) my IO pads on the chip... i also included .io file when i import my design.
 
Parents

  •  Hi..

      Thanks for your reply. I dnt have NCSIM . So is there any more chance for me to generate vcd file with modelsim/xilinx .. And i also need osme help in generating Power grid librarry i.e .cl file. Do you know hoew to generate ./ i saw the user guide but there was nothing regarding .cl file generation ? so if u can help me i will be really lucky. And comming to io pads, i dnt have my io pads in my netlist. So if u can say me how to include in the net list i would be really happy. With a small example for a 4 bit adder. or any other simple .verilog code.

Reply

  •  Hi..

      Thanks for your reply. I dnt have NCSIM . So is there any more chance for me to generate vcd file with modelsim/xilinx .. And i also need osme help in generating Power grid librarry i.e .cl file. Do you know hoew to generate ./ i saw the user guide but there was nothing regarding .cl file generation ? so if u can help me i will be really lucky. And comming to io pads, i dnt have my io pads in my netlist. So if u can say me how to include in the net list i would be really happy. With a small example for a 4 bit adder. or any other simple .verilog code.

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