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  3. Reg static and dynamic Power Analysis

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Reg static and dynamic Power Analysis

Music
Music over 15 years ago

Hi...

I would like to knwo the steps included in finding out Static and dynamic Power analysis in SoC Encounter 8.1

I have a design.v, design_synth.v, .lib file, .lef file, .sdf file .So please let me know how to get the power .. include the steps plz...

how can i view(from GUI) my IO pads on the chip... i also included .io file when i import my design.
 
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  • gops
    gops over 15 years ago
    Hello;

    I'm not sure about modelsim/xilinx.I think the following is enough for modelsim also.you can give it in modelsim prompt(VSIM) corresponding to ncsim in NC.I am not so familiar with modelsim,sorry if there is some error.

    vcd file myvcdfile.vcd

    vcd add /test_name/dut/*

    run

    quit -f

    But for generating powergrid views you need Encounter power system (EPS) license.Do you have EPS license?check the EPS documentation regarding .cl file generation.

    Regarding IO pad insertion there are two ways to do it.The simple way is to create another top level in RTL code, with ports connceted to IOcells and then synthesize.

    Another is reading the synthesized n/l in virtuso and insert padcells in virtouso and write out the pad inserted n/l ..

    I think you can use the first method. attached is a simple example how to create a top level with pad instantiation.I haven't checked the syntax of the code.there may be some errors.But i think this is enough to give you the idea.

    gops
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  • gops
    gops over 15 years ago
    Hello;

    I'm not sure about modelsim/xilinx.I think the following is enough for modelsim also.you can give it in modelsim prompt(VSIM) corresponding to ncsim in NC.I am not so familiar with modelsim,sorry if there is some error.

    vcd file myvcdfile.vcd

    vcd add /test_name/dut/*

    run

    quit -f

    But for generating powergrid views you need Encounter power system (EPS) license.Do you have EPS license?check the EPS documentation regarding .cl file generation.

    Regarding IO pad insertion there are two ways to do it.The simple way is to create another top level in RTL code, with ports connceted to IOcells and then synthesize.

    Another is reading the synthesized n/l in virtuso and insert padcells in virtouso and write out the pad inserted n/l ..

    I think you can use the first method. attached is a simple example how to create a top level with pad instantiation.I haven't checked the syntax of the code.there may be some errors.But i think this is enough to give you the idea.

    gops
    • test.txt
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