How to handle assign statements

Try adding tie cells before writing verilog.
If you work with RTL - Compiler it looks like:
remove_assigns
insert_tiehilo_cells

Hi Stalker,

The ASIC vendors that we are dealing with do not have TieHi/TieLo cells in their library. So we need to connect these nets directly to vdd/gnd. Is there a way to do this, either in SoCE or RTL-C.

Thanks;
Krishna

I never connected cells directly to the grid.
As far as I know LVS tools recognize 1'b0/1'b1 as vss/vdd

so can we leave the nets floating. i thought there is a way to connect all 1'b0 to gnd and 1'b1 to vdd.

Hi Krishna,

Make sure you have the following in your .conf file before loading the design: (NOTE this is an example; make sure to use your specific pwr/gnd net names and std cell pin names. These are usually VDD/VSS, but can be different.)

set rda_Input(ui_pg_connections) [list \
{PIN:VDD:} \
{PIN:VSS:} \
{TIEHI::} \
{TIELO::} \
]
set rda_Input(PIN:VDD:) {VDD}
set rda_Input(PIN:VSS:) {VSS}
set rda_Input(TIEHI::) {VDD}
set rda_Input(TIELO::) {VSS}

This should setup tiehi/lo nets and nanoroute should connect them.

Hope that helps,

- Kari

Thanks Kari. It worked.

You're welcome, Krishna. I'm glad that worked for you.

- Kari

Hi Kari/ Krishna,

In this, I understand that VDD and VSS are the power and ground nets. But, what are "TIEHI::" and "TIELO::" keyword?

Sorry for this stupid question. But I am facing the same problem.

Regards,

Pramod

 Hi Pramod,

There are no stupid questions! :-)

The TIEHI and TIELO keywords are just saying that pins tied high (1'b1) will be connected to VDD, and those tied low (1'b0) will be tied to VSS. Your pwr/gnd names may be different, but the keywords TIEHI and TIELO do not change here.

Hope that helps,

- Kari