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How to handle assign statements

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In our design, we have few signals which need to be tied to 1'b0, 1'b1, as shown below.

    assign z[16] = 1'b0 ;
    assign port_comp[0] = 1'b1;

During PD, I want to tie these nets to VDD and GND nets. Can somebody help on how to do this?

Thanks in Advance,
Krishna


Originally posted in cdnusers.org by gukumar
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