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clock tree levels and gating

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Hi,

I have tried SOC62, and have noticed that as soon as I add clock gating in RC, the number of clock tree levels blows out, in my case from 6 levels to 22.
I have tried all sorts of options and commands in the clock spec file, but the levels don't change much.
The gating happens very close to the root, and one would think that it should add just a couple of extra levels not 15.
What's worse is that with gating the skews also become a lot worse.

Is this normal?

Thanks
AA


Originally posted in cdnusers.org by aus_amx
Parents

  • Hi mboudreaux,

    Have you tried to leverage SoC-Encounter's Integrated Clock Gating Cell cloning capability ("ckCloneGate")? In scenarios where there are multiple levels of clock gating with different enable signals, "setPlaceMode -clkGateAware true" has limited effectiveness in my experience.

    Thanks,
    Bob


    Originally posted in cdnusers.org by BobD
Reply

  • Hi mboudreaux,

    Have you tried to leverage SoC-Encounter's Integrated Clock Gating Cell cloning capability ("ckCloneGate")? In scenarios where there are multiple levels of clock gating with different enable signals, "setPlaceMode -clkGateAware true" has limited effectiveness in my experience.

    Thanks,
    Bob


    Originally posted in cdnusers.org by BobD
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