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Power port connection

Greatrebel

Hi all,

 I have some problem with power/ground port connection. The problem is that when I did special routing, the power and ground were not connected. I got some clue from Encounter log to check my netlist. So I instantiated power and ground cells under the top module which is a dummy module and includes all IO cells and the core design module.

I added two pins in the pin list of the top module as well, called VDD_PIN and VSS_PIN. In my design, the global power/ground net are called VDD/VSS. The power pad cell has two inout ports, I connected one of them to the VDD_PIN. For the other one, according to the specification, it should be connected to core. But I do not know where I should connect it to. If I connect it to the power net VDD, I will get a warning saying "This can create a short circuit if the output is 0.  Check the connectivity in the netlist." So I just leave it floating.

 When I tried to connect power/ground port to global net VDD/VSS by using 

GlobalNetConnection: VDD -pin VDD_PIN -inst * -type pgpin -module {}
GlobalNetConnection: VSS -pin VSS_PIN -inst * -type pgpin -module {}

I got errors below:

A global net connection rule for connecting P/G pins of the pattern 'VDD_PIN' was specified.  But the connections cannot be made because there is no such pin in any cell.  Check the pin name pattern and make sure it is correct.

A global net connection rule for connecting P/G pins of the pattern 'VSS_PIN' was specified.  But the connections cannot be made because there is no such pin in any cell.  Check the pin name pattern and make sure it is correct.

Any help for how to connect power/ground ports will be greatly appreciated.

 

Thanks in advanced

Wei

Parents

  •  The std cell pwr/gnd pins and their connections do not usually appear in the verilog netlist. That's why you have to use globalNetConnect to set these up. If you look in the LEF file of the std cells, you should see the pwr/gnd pins defined. They will be USE POWER or USE GROUND. When the std cell is in the floorplan in the Encounter window, you can see the pwr/gnd rails of the cell. If you turn on the Q button at the bottom of the Encounter window, and hover the mouse pointer over the std cell pwr/gnd rail, you can look at the bottom of the window and see if the connection to those pins is NULL (global nets are not set correctly), or VDD/VSS (global nets are set correctly). Hope that helps!

Reply

  •  The std cell pwr/gnd pins and their connections do not usually appear in the verilog netlist. That's why you have to use globalNetConnect to set these up. If you look in the LEF file of the std cells, you should see the pwr/gnd pins defined. They will be USE POWER or USE GROUND. When the std cell is in the floorplan in the Encounter window, you can see the pwr/gnd rails of the cell. If you turn on the Q button at the bottom of the Encounter window, and hover the mouse pointer over the std cell pwr/gnd rail, you can look at the bottom of the window and see if the connection to those pins is NULL (global nets are not set correctly), or VDD/VSS (global nets are set correctly). Hope that helps!

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