Power port connection

 Hi Wei,

What are the names of the pwr/gnd pins of your std cells? (Usually something like VDD and VSS.) This is what you need in the globalNetConnect statement.

globalNetConnect VDD   -type pgpin -pin VDD  -inst * -all -override

I don't think you needed to create those VDD_PIN and VSS_PIN pins. You should have several pwr/gnd IO cells in your design and that is where the pwr/gnd nets originate from. The core-facing pin of these IO cells (usually much larger than a signal pin) will connect to the power grid that you create. 

Get the globalNetConnect statments going, then try again to route your pwr/gnd.

- Kari

do you mean the stdcell's verilog file which includes the VDD and VSS should be selected in PNR stage ?

 The std cell pwr/gnd pins and their connections do not usually appear in the verilog netlist. That's why you have to use globalNetConnect to set these up. If you look in the LEF file of the std cells, you should see the pwr/gnd pins defined. They will be USE POWER or USE GROUND. When the std cell is in the floorplan in the Encounter window, you can see the pwr/gnd rails of the cell. If you turn on the Q button at the bottom of the Encounter window, and hover the mouse pointer over the std cell pwr/gnd rail, you can look at the bottom of the window and see if the connection to those pins is NULL (global nets are not set correctly), or VDD/VSS (global nets are set correctly). Hope that helps!

Hi Kari,

 Thank you very much for your help. Now I have already connected std cell pwr/gnd pins to global pwr/gnd nets. But I still got some warning after special routing as follows:

**WARN: (SOCSR-1254): Net VDD does not have block pins to be routed. Please check net list.
**WARN: (SOCSR-1255): Net VDD does not have pad pins to create pad ring. Please check net list or port class. (must NOT be CORE class and must not be AREAIO subclass).
**WARN: (SOCSR-1254): Net VSS does not have block pins to be routed. Please check net list.
**WARN: (SOCSR-1255): Net VSS does not have pad pins to create pad ring. Please check net list or port class. (must NOT be CORE class and must not be AREAIO subclass).

How can I fix those warnings.

Also for I/O voltage, I instantiated a pwr IO cell for I/O voltage 2.5 v. I am wondering do I need to create a global net for this I/O voltage?

 Thanks a lot

 On the sroute form, there are many options of things to connect. It looks like you may be selecting the options to connect blocks and IO cells without meaning to. (Blocks would be non-std cell macros, like RAMs, analog blocks, or other IP.) If you don't have any blocks but told sroute to route to them, then you would see this warning. You can probably ignore it, but I understand you wanting a clean run with no warning messages.

As for the IOs, it looks like you may be trying to create a pad ring - I'd have to check the sroute options for that. But take a closer look at the form (I'm assuming you're using the gui and not command-line), and make sure you only have the things checked that you really want to connect.

For your IO voltage, if you have components in your design that will connect to a 2.5v source, then you probably need a global connect statement for those. If it's only the IO power that is 2.5v, then that is usually taken care of by the IO cells abutting each other, and you don't have to do anything. It's hard to say without knowledge of your design though.

 Hi Kari,

I am not very sure about what the pad ring is. Does this pad mean I/O pad or bond pad. At current stage, I have no bond pads but I/O pads, so I am not sure whether I need pad ring or not.  For the tie-high and tie-low pins of I/O cells, should I connect them to VDD/VSS net at core voltage?

Thanks a lot

 The pad ring is for the IO pads. It's the pwr/gnd ring that is usually created simply by the abutment of your IO cells around the chip (with IO filler cells filling any gap). Some designs may have unique configurations, but in general, this is how it works. The IO cells will have wide pins that span the width of the cell, so that they touch the same pin on the cell they are next to, thus creating the ring. These pins may or may not be defined in your IO LEF file, so you may or may not be able to see them in Encounter. Usually, they are defined though. See if they are present in your design. If this "ring" is created by abutment of the IO cells, then you don't need to use sroute to create it.

 As for the tiehi/lo pins of the IO cells, if you mean small pins that face the core of the design that are tied hi or lo because they are not used for signals, then yes - these should be connected to the core pwr/gnd nets. However, sroute is not used for these connections. The tiehi/lo nets are actually "regular nets", not special nets. When you nanoroute the design, nanoroute will connect these.

I understand now. Thank you very much for your help.

Hey Kari,

I have been searching all over, but can't seem to find an answer to my issue, but this seems close.  I have no issue connecting my VDD18 and VSS to my macros and std cells, but in this current iteration of my design, I have a SRAM and 45 std cells that I need to connect to a different power source.  The issue is that the power source, called VBATT is an input from one of the I/O pads.  Every time I use globalNetConnect VBATT -pin VDD -type pigpen -inst "instance path/*" -override, but when I run sroute with just the area I fenced these cells into after placing rings and stripes, the VDD pin in the SRAM still only wants to connect to VDD18, my global VDD and not the signal power source VBATT I am trying to attach it to.  Any help would be appreciated.