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Power port connection

Greatrebel

Hi all,

 I have some problem with power/ground port connection. The problem is that when I did special routing, the power and ground were not connected. I got some clue from Encounter log to check my netlist. So I instantiated power and ground cells under the top module which is a dummy module and includes all IO cells and the core design module.

I added two pins in the pin list of the top module as well, called VDD_PIN and VSS_PIN. In my design, the global power/ground net are called VDD/VSS. The power pad cell has two inout ports, I connected one of them to the VDD_PIN. For the other one, according to the specification, it should be connected to core. But I do not know where I should connect it to. If I connect it to the power net VDD, I will get a warning saying "This can create a short circuit if the output is 0.  Check the connectivity in the netlist." So I just leave it floating.

 When I tried to connect power/ground port to global net VDD/VSS by using 

GlobalNetConnection: VDD -pin VDD_PIN -inst * -type pgpin -module {}
GlobalNetConnection: VSS -pin VSS_PIN -inst * -type pgpin -module {}

I got errors below:

A global net connection rule for connecting P/G pins of the pattern 'VDD_PIN' was specified.  But the connections cannot be made because there is no such pin in any cell.  Check the pin name pattern and make sure it is correct.

A global net connection rule for connecting P/G pins of the pattern 'VSS_PIN' was specified.  But the connections cannot be made because there is no such pin in any cell.  Check the pin name pattern and make sure it is correct.

Any help for how to connect power/ground ports will be greatly appreciated.

 

Thanks in advanced

Wei

Parents

  •  The pad ring is for the IO pads. It's the pwr/gnd ring that is usually created simply by the abutment of your IO cells around the chip (with IO filler cells filling any gap). Some designs may have unique configurations, but in general, this is how it works. The IO cells will have wide pins that span the width of the cell, so that they touch the same pin on the cell they are next to, thus creating the ring. These pins may or may not be defined in your IO LEF file, so you may or may not be able to see them in Encounter. Usually, they are defined though. See if they are present in your design. If this "ring" is created by abutment of the IO cells, then you don't need to use sroute to create it.

     As for the tiehi/lo pins of the IO cells, if you mean small pins that face the core of the design that are tied hi or lo because they are not used for signals, then yes - these should be connected to the core pwr/gnd nets. However, sroute is not used for these connections. The tiehi/lo nets are actually "regular nets", not special nets. When you nanoroute the design, nanoroute will connect these.

Reply

  •  The pad ring is for the IO pads. It's the pwr/gnd ring that is usually created simply by the abutment of your IO cells around the chip (with IO filler cells filling any gap). Some designs may have unique configurations, but in general, this is how it works. The IO cells will have wide pins that span the width of the cell, so that they touch the same pin on the cell they are next to, thus creating the ring. These pins may or may not be defined in your IO LEF file, so you may or may not be able to see them in Encounter. Usually, they are defined though. See if they are present in your design. If this "ring" is created by abutment of the IO cells, then you don't need to use sroute to create it.

     As for the tiehi/lo pins of the IO cells, if you mean small pins that face the core of the design that are tied hi or lo because they are not used for signals, then yes - these should be connected to the core pwr/gnd nets. However, sroute is not used for these connections. The tiehi/lo nets are actually "regular nets", not special nets. When you nanoroute the design, nanoroute will connect these.

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