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A CTS error: The net clk is driven by more than one driver.

Greatrebel

Hi All,

 I got an error when I do clock tree synthesis in Encounter

**ERROR: (SOCCK-218):   The net clk is driven by more than one driver. Please correct your clock specification file to exclude the net.
**ERROR: (SOCCK-211):   CTS was unable to trace clock clk.

I checked the clock specification file, but I do not have any clue where causes this multiple drivers. Below is my clock spec. Please give me a help

 AutoCTSRootPin clk
Period         5ns
MaxDelay       0.5ns # set_clock_latency
MinDelay       0.5ns # set_clock_latency
MaxSkew        200ps # set_clock_uncertainty
SinkMaxTran    200ps # set_clock_transition
BufMaxTran     200ps # set_clock_transition
Buffer         CKBHVTD2 CKBHVTD3 CKBHVTD4 CKBHVTD6 CKBHVTD8 CKNHVTD6 CKNHVTD8 CKNHVTD12 CKNHVTD16 CKNHVTD0
NoGating       NO
DetailReport   YES
SetDPinAsSync  YES
#SetIoPinAsSync NO
RouteClkNet    YES
PostOpt        YES
OptAddBuffer   YES
#RouteType      specialRoute
#LeafRouteType  regularRoute
ThroughPin
END

 

Parents

  •  Your clock spec looks fine, I don't think that's the problem. Check your netlist, specifically the net attached to pin "clk". You can use the Design Browser in Encounter to trace through the net, starting from the pin, if you prefer that to looking at the actual verilog or DEF netlist. (Tools->Design Browser). 

Reply

  •  Your clock spec looks fine, I don't think that's the problem. Check your netlist, specifically the net attached to pin "clk". You can use the Design Browser in Encounter to trace through the net, starting from the pin, if you prefer that to looking at the actual verilog or DEF netlist. (Tools->Design Browser). 

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