A CTS error: The net clk is driven by more than one driver.

 Your clock spec looks fine, I don't think that's the problem. Check your netlist, specifically the net attached to pin "clk". You can use the Design Browser in Encounter to trace through the net, starting from the pin, if you prefer that to looking at the actual verilog or DEF netlist. (Tools->Design Browser). 

 I checked the Design Browser, there is one terminal and one net called clk under the top module. I checked the net clk, there are two pins associated with it. One is clk (input) - clk and the other is IOCELL42/PAD (bidir). I think this bidirectional pin causes the multiple drive. This pin from the I/O pad. In my netlist, I have a top module where instanciates both I/O cells and the core design cell. I have my clock connected like something shown below.

module top_module (port list);

....

input clk;

wire IO42;

PRUW1216SCDG_25 IOCELL42( .I(1'b0),.DS(1'b1),.OEN(1'b1),.PAD(clk),.C(IO42),.PE(1'b1),.IE(1'b1));

core_design core (.clk(IO42) ....);

for I/O cell, PAD->C is input path. Could you please tell me whether it is the correct way to connect I/O with the core cell. From the layout, the C port of the I/O pad is not connected to the core cell.

Also I found there are a lot of unplaced I/O pins, how I can place those I/O pin. I have already load I/O assignment file which assign all I/O pad cells.

Thank you a lot

 So, if I understand correctly - the clock signal comes into the chip on the PAD pin of this IO. Then it must exit the IO into the core of the chip. You say that would be the C pin of the IO. But the net connected to the C pin is something called IO42. 

Typically, the clock net will have one input (either a pin if you're working on a block, or an IO if you're working on a chip), and MANY outputs - all the registers that are clocked by that clock signal. When you build the clock tree, you add buffering to break up that one large fanout net into many subnets. So it looks to me like your clock net is not set up right in the netlist yet. Unless, the net IO42 is really the clock net. Check the design browser for that net. Does it go to many clock pins of flops?

I am designing a chip, so I need an IO as the clock input. As shown in the code, the net IO42 is connected to the clk input of the core cell. I checked IO42, it connected to the clock pins of flops. But when I checked the clk net in the top module, it did not highlight any wire, just highlighted the two pins connected to it. And there is no any timing information generated, all zero.  But if I directly connect clk input of top module to the clk input of core cell without connecting to the IO, I can get the timing information saying how many setup and hold violation.

thanks 

 In your top level Design, is IO42 the input port? If it is, then you should tie pad of IO cell to 'IO42' instead of 'clk'. Then tie .C(clk) of IO cell and core_design core (.clk(clk) ....). Then try running the clock tree synthesis. 

If 'clk' is indeed the input port in your top level design, then your connection is correct. Then you should modify your clock specification file to make core side of IO cell as the root of clock tree, not the pad side.

so instead of   'AutoCTSRootPin clk' you will have  'AutoCTSRootPin IOCELL42/C'. 

I hope this helps.