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A CTS error: The net clk is driven by more than one driver.

Greatrebel

Hi All,

 I got an error when I do clock tree synthesis in Encounter

**ERROR: (SOCCK-218):   The net clk is driven by more than one driver. Please correct your clock specification file to exclude the net.
**ERROR: (SOCCK-211):   CTS was unable to trace clock clk.

I checked the clock specification file, but I do not have any clue where causes this multiple drivers. Below is my clock spec. Please give me a help

 AutoCTSRootPin clk
Period         5ns
MaxDelay       0.5ns # set_clock_latency
MinDelay       0.5ns # set_clock_latency
MaxSkew        200ps # set_clock_uncertainty
SinkMaxTran    200ps # set_clock_transition
BufMaxTran     200ps # set_clock_transition
Buffer         CKBHVTD2 CKBHVTD3 CKBHVTD4 CKBHVTD6 CKBHVTD8 CKNHVTD6 CKNHVTD8 CKNHVTD12 CKNHVTD16 CKNHVTD0
NoGating       NO
DetailReport   YES
SetDPinAsSync  YES
#SetIoPinAsSync NO
RouteClkNet    YES
PostOpt        YES
OptAddBuffer   YES
#RouteType      specialRoute
#LeafRouteType  regularRoute
ThroughPin
END

 

Parents

  • I am designing a chip, so I need an IO as the clock input. As shown in the code, the net IO42 is connected to the clk input of the core cell. I checked IO42, it connected to the clock pins of flops. But when I checked the clk net in the top module, it did not highlight any wire, just highlighted the two pins connected to it. And there is no any timing information generated, all zero.  But if I directly connect clk input of top module to the clk input of core cell without connecting to the IO, I can get the timing information saying how many setup and hold violation.

     

    thanks 

Reply

  • I am designing a chip, so I need an IO as the clock input. As shown in the code, the net IO42 is connected to the clk input of the core cell. I checked IO42, it connected to the clock pins of flops. But when I checked the clk net in the top module, it did not highlight any wire, just highlighted the two pins connected to it. And there is no any timing information generated, all zero.  But if I directly connect clk input of top module to the clk input of core cell without connecting to the IO, I can get the timing information saying how many setup and hold violation.

     

    thanks 

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