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A CTS error: The net clk is driven by more than one driver.

Greatrebel

Hi All,

 I got an error when I do clock tree synthesis in Encounter

**ERROR: (SOCCK-218):   The net clk is driven by more than one driver. Please correct your clock specification file to exclude the net.
**ERROR: (SOCCK-211):   CTS was unable to trace clock clk.

I checked the clock specification file, but I do not have any clue where causes this multiple drivers. Below is my clock spec. Please give me a help

 AutoCTSRootPin clk
Period         5ns
MaxDelay       0.5ns # set_clock_latency
MinDelay       0.5ns # set_clock_latency
MaxSkew        200ps # set_clock_uncertainty
SinkMaxTran    200ps # set_clock_transition
BufMaxTran     200ps # set_clock_transition
Buffer         CKBHVTD2 CKBHVTD3 CKBHVTD4 CKBHVTD6 CKBHVTD8 CKNHVTD6 CKNHVTD8 CKNHVTD12 CKNHVTD16 CKNHVTD0
NoGating       NO
DetailReport   YES
SetDPinAsSync  YES
#SetIoPinAsSync NO
RouteClkNet    YES
PostOpt        YES
OptAddBuffer   YES
#RouteType      specialRoute
#LeafRouteType  regularRoute
ThroughPin
END

 

Parents

  •  So, if I understand correctly - the clock signal comes into the chip on the PAD pin of this IO. Then it must exit the IO into the core of the chip. You say that would be the C pin of the IO. But the net connected to the C pin is something called IO42. 

    Typically, the clock net will have one input (either a pin if you're working on a block, or an IO if you're working on a chip), and MANY outputs - all the registers that are clocked by that clock signal. When you build the clock tree, you add buffering to break up that one large fanout net into many subnets. So it looks to me like your clock net is not set up right in the netlist yet. Unless, the net IO42 is really the clock net. Check the design browser for that net. Does it go to many clock pins of flops?

Reply

  •  So, if I understand correctly - the clock signal comes into the chip on the PAD pin of this IO. Then it must exit the IO into the core of the chip. You say that would be the C pin of the IO. But the net connected to the C pin is something called IO42. 

    Typically, the clock net will have one input (either a pin if you're working on a block, or an IO if you're working on a chip), and MANY outputs - all the registers that are clocked by that clock signal. When you build the clock tree, you add buffering to break up that one large fanout net into many subnets. So it looks to me like your clock net is not set up right in the netlist yet. Unless, the net IO42 is really the clock net. Check the design browser for that net. Does it go to many clock pins of flops?

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