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A CTS error: The net clk is driven by more than one driver.

Greatrebel

Hi All,

 I got an error when I do clock tree synthesis in Encounter

**ERROR: (SOCCK-218):   The net clk is driven by more than one driver. Please correct your clock specification file to exclude the net.
**ERROR: (SOCCK-211):   CTS was unable to trace clock clk.

I checked the clock specification file, but I do not have any clue where causes this multiple drivers. Below is my clock spec. Please give me a help

 AutoCTSRootPin clk
Period         5ns
MaxDelay       0.5ns # set_clock_latency
MinDelay       0.5ns # set_clock_latency
MaxSkew        200ps # set_clock_uncertainty
SinkMaxTran    200ps # set_clock_transition
BufMaxTran     200ps # set_clock_transition
Buffer         CKBHVTD2 CKBHVTD3 CKBHVTD4 CKBHVTD6 CKBHVTD8 CKNHVTD6 CKNHVTD8 CKNHVTD12 CKNHVTD16 CKNHVTD0
NoGating       NO
DetailReport   YES
SetDPinAsSync  YES
#SetIoPinAsSync NO
RouteClkNet    YES
PostOpt        YES
OptAddBuffer   YES
#RouteType      specialRoute
#LeafRouteType  regularRoute
ThroughPin
END

 

Parents

  •  I checked the Design Browser, there is one terminal and one net called clk under the top module. I checked the net clk, there are two pins associated with it. One is clk (input) - clk and the other is IOCELL42/PAD (bidir). I think this bidirectional pin causes the multiple drive. This pin from the I/O pad. In my netlist, I have a top module where instanciates both I/O cells and the core design cell. I have my clock connected like something shown below.

    module top_module (port list);

    ....

    input clk;

    wire IO42;

    PRUW1216SCDG_25 IOCELL42( .I(1'b0),.DS(1'b1),.OEN(1'b1),.PAD(clk),.C(IO42),.PE(1'b1),.IE(1'b1));

    core_design core (.clk(IO42) ....);

    for I/O cell, PAD->C is input path. Could you please tell me whether it is the correct way to connect I/O with the core cell. From the layout, the C port of the I/O pad is not connected to the core cell.

    Also I found there are a lot of unplaced I/O pins, how I can place those I/O pin. I have already load I/O assignment file which assign all I/O pad cells.

    Thank you a lot

Reply

  •  I checked the Design Browser, there is one terminal and one net called clk under the top module. I checked the net clk, there are two pins associated with it. One is clk (input) - clk and the other is IOCELL42/PAD (bidir). I think this bidirectional pin causes the multiple drive. This pin from the I/O pad. In my netlist, I have a top module where instanciates both I/O cells and the core design cell. I have my clock connected like something shown below.

    module top_module (port list);

    ....

    input clk;

    wire IO42;

    PRUW1216SCDG_25 IOCELL42( .I(1'b0),.DS(1'b1),.OEN(1'b1),.PAD(clk),.C(IO42),.PE(1'b1),.IE(1'b1));

    core_design core (.clk(IO42) ....);

    for I/O cell, PAD->C is input path. Could you please tell me whether it is the correct way to connect I/O with the core cell. From the layout, the C port of the I/O pad is not connected to the core cell.

    Also I found there are a lot of unplaced I/O pins, how I can place those I/O pin. I have already load I/O assignment file which assign all I/O pad cells.

    Thank you a lot

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