Short between IO filler blockage and IO pad pin

Hi,

In our design we have IO fillers with blockage for the IO ring power & ground stripes, and IO pads with pins for the same busses. When placing fillers between the IO cells, we see short violations between the pad pins and the filler blockages (see attached image). How can we fix or ignore these violations?

The LEF for the IO filler and pad looks like:

MACRO IOFILLER
    ...
    OBS
        LAYER M3 ;
        RECT  0.00 78.50 5.60 104.06 ;
   ...


MACRO IOPAD
    CLASS PAD ;
    SITE IO ;
    PIN VDD!
        DIRECTION INOUT ;
        USE POWER ;
        PORT
        LAYER M3 ;
        RECT  0.00 78.82 75.04 83.58 ;
..

Link to GUI image: http://i42.tinypic.com/33di5jc.gif

Thanks in advance,

/Max