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Floating gates !

Amr Zahir
I'm using SoC Encounter 8.1, with IBM 130nm std cell library. When I submit my layout to foundry it reports (floating gates)...exactly twice the number of std cells used ! So my questions are; do I have to tie the substrate & wells to power pins by hand or it's tied internally in the cell ? And what about ENDCAP cells...can they report such violations if they don't exist ? Note that Encounter reports no errors (there's no Unconnected pins in the design) Thank you

  •  Some std cell libraries have the well ties as part of the cell, and with others, you have to use well tap cells. These are cells that are included in the library that you have to array out in the design at a specific spacing to satisfy the well tie rules for your process. Endcap cells may or may not also be required. Chances are, if welltaps and endcaps are in your std cell library, they are there for a reason. :-) Check your design process manual or std cell library documentation for more info.

  • Thanks Kari Actually I don't have (ENDCAP) or (well tap) cells in my library. I want to know if floating substrate & NWELL can make this (floating gate) violation ?!

  • Without being familiar with your design's process and DRC/LVS decks, I can't really say. The foundry should be able to give you some more detail about why this error is occurring.

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